針對提高可靠性之容錯矽穿通道架構評估

Architectural Evaluations on TSV Redundancy for Reliability Enhancement

邱建邦(Chiu, Chien Pang)

指導教授 ： 黃婷婷

國立清華大學/電機資訊學院/資訊工程學系/碩士(2016年)

摘要

三維積體電路被認為是可以克服晶片電晶體數量不足問題的方法，三維積 體電路是利用矽穿通道來做晶粒的推疊，讓訊號可以在晶片上垂直地傳輸。但是晶片在運作時可能導致矽穿通道的毀壞，因此，可靠性在設計時是很重要的議題。容錯矽穿通道設計是一個提升可靠性的有效方法。在這篇論文中，我們會根據效率與成本來研究各種容錯矽穿通道設計的權衡取捨。為了讓可靠性的測量更具有真實性，我們提出了一個新的標準「修復率」來評估容錯矽穿通道設計的好壞。此外，為了設計一個更靈活且更有效的架構，我們加強環狀結構設計 [1]，讓這個架構可以調整大小以及容錯矽穿通道的比例。

關鍵字

矽穿通道 ； 容錯 ； 可靠性

並列摘要

Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can transmit through dies vertically. TSV may fail when a chip is working. Hence, reliability is an important issue in design time. TSV redundancy is one of effective methods to enhance reliability. In this paper, we will study the tradeoff of various TSV redundancy architectures in terms of effectiveness and cost. To allow the measurement of reliability more realistic, we propose a new standard, repair rate, to appraise the TSV redundancy architectures. Moreover, to design a more flexible and efficient structure, we enhance the ring-based architecture [1] that can adjust grid size and TSV redundancy.

並列關鍵字

TSV ； redundancy ； reliability

參考文獻

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[3] YC Tan, Cher Ming Tan, XW Zhang, Tai Chong Chai, and DQ Yu. Electromigration performance of through silicon via (tsv)-a modeling approach. Microelectronics

[4] Mohit Pathak, Jiwoo Pak, David Z Pan, and Sung Kyu Lim. Electromigration modeling and full-chip reliability analysis for beol interconnect in tsv-based 3d ics. In Proceedings of the International Conference on Computer-Aided Design, pages 555-562. IEEE Press, 2011.

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[7] Ang-Chih Hsieh and TingTing Hwang. Tsv redundancy: architecture and design issues in 3-d ic. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on,