垂直閘極形式三維NAND快閃記憶體技術之電性研究

Electrical Study of Vertical Gate (VG) Type 3D NAND Flash Memory Technology

葉騰豪(Teng-Hao Yeh)

指導教授 ： 金雅琴 ； 施彥豪

國立清華大學/電機資訊學院/電子工程研究所/博士(2016年)

摘要

在NAND快閃記憶體發展歷史當中，由更高的密度來降低晶片成本一直是驅動此一技術演變的主要動力。以傳統平面式NAND快閃記憶體而言，當關鍵尺寸(Critical Dimension, CD)微縮到十奈米時，持續劣化的晶胞(cell)元件特性以及自對準四重圖案(Self Aligned Quadruple Patterning, SAQP)製程將會是此技術開發的主要挑戰。為了能持續追求更具競爭力的NAND快閃記憶體，近年來，三維NAND快閃記憶體技術發展迅速。由於三維NAND記憶體可以採用較大的晶胞尺寸來改善晶胞元件特性，而且利用所謂的”多重堆疊一次蝕刻”的概念，可以得到更低的位元成本(bit-cost)。因此，有別於傳統NAND快閃記憶體技術僅在平面方向上的微縮，三維NAND快閃記憶體將多層記憶體垂直堆疊起來，再利用一次性的深蝕刻獨立出各個單位晶胞，以達到更佳的元件表現和更具競爭力的生產成本，進而讓NAND快閃記憶體技術持續微縮下去且同時符合經濟效益。
在眾多三維NAND快閃記憶體當中，每種架構都有各自的優缺點。首先，本研究先針對不同架構進行評估發現，採用水平電流流動方式的垂直閘極(Vertical Gate, VG)形式三維NAND快閃記憶體除了微縮平面關鍵尺寸佔有優勢之外，其架構的讀取電流也不因堆疊層數增加而降低。因此，本研究選定以垂直閘極形式架構為主軸，並針對此架構衍生的特殊效應進行一系列的分析以及優化。在本研究的第二章將介紹垂直閘極形式三維NAND快閃記憶體的設計與結構，包含其操作與選取晶胞之方法。
本論文第三章先探討垂直閘極形式三維NAND的陣列效率(array efficiency)，並藉由改變晶胞串(NAND string)的架構來提高平面的陣列效率，本章中先回顧Chen等人先前提出的”分割頁”(split-page)架構以及其陣列效率，接著本章再提出交錯狀閘極(stagger gate)的新架構來減少串選擇線(string select line, SSL)佔據陣列的比例，此新架構可以將原本只有71%的陣列效率提升至81%。此外，此研究也針對這種新的串選擇線架構的操作方式和電性表現作一詳盡的探討，提供日後能設計出更具成本競爭力的垂直閘極形式三維NAND快閃記憶體。
在三維記憶體製程當中，一次性的深蝕刻必須確保所有晶胞能夠被獨立分離，關鍵的製程能力就是其蝕刻機台所能達到的最大深寬比值(Aspect Ratio)，因此，在不改變蝕刻製程能力的前提下，進一步微縮每一層薄膜的厚度將會得到更高的記憶體密度。本研究第四章利用2層架構的元件進行垂直間距(Z-pitch)的微縮實驗。研究中發現，雖然實驗成功將垂直間距從60奈米縮小到18奈米，但卻也遭遇到記憶容限度(memory margin)衰退以及讀取電流降低的問題。對於記憶容限度衰退的機制，垂直干擾(Z-interference)以及垂直擾動(Z-disturbance)等兩種不同機制能夠完整解釋抑制電晶體(inhibited transistor)的臨限電壓(threshold voltage)之改變，其中又以垂直干擾為主要影響記憶容限度的機制，本論文將在第五章更深入地研究垂直干擾，實際量測8層結構的元件，輔以模擬的結果提出一組合適的垂直間距當作基準，並進一步探討如何減少垂直干擾以及增加記憶容限度的可行方法。
除了垂直間距會直接改變元件特性之外，水平方向上的距離也同樣對元件有重要影響。其中，一個重要的參數是邊緣字元線(edge word line)到接地選擇線(ground select line, GSL)或到串選擇線(SSL)的距離，第六章探討此距離大小對於垂直閘極形式三維NAND陣列在操作上的影響，包含讀取電流(sensing current)，寫入抑制(programming inhibition)，以及刪除速度(erasing speed)等電性差異，透過實驗和模擬的結果也歸納出最適合的距離作為此架構之設計準則。
最後，在第七章根據前面的主題以及結果，整理出垂直閘極形式三維NAND快閃記憶體在製作上以及設計上的重要準則，同時間，藉由此研究過程也將更加了解此技術的優勢以及其限制。

關鍵字

三維結構 ； 快閃記憶體 ； 半導體技術 ； 薄膜電晶體 ； 電荷儲存元件

並列摘要

Throughout the technology development history of NAND Flash memory, the lower chip cost achieved by higher density array is the main driving force for further evolution. For conventional planar 2D NAND, when the critical dimension (CD) is shrunk to 10nm node, it will inevitably encounter numerous challenges in terms of degraded device performance and complex process modules, such as SAQP (Self-Aligned Quadruple Patterning) scheme. In order to keep pursuing more competitive NAND Flash memory, 3D (three dimensional) NAND Flash technology has been rapidly developed in recent years. 3D NAND Flash memory can improve the device performance by designing a larger cell size. Moreover, it can also achieve lower bit-cost based on the concept of “multiple-layer stack and one critical etching”. Unlike the cell size is relentlessly shrunk in the conventional NAND technology, the 3D NAND Flash memory stacks plural memory layers with relaxed cell size and divides each device by a deep etching scheme, which makes it as a high performance and low cost chip. Via this concept, NAND technology could be effectively scaled in an economic way.
Among the 3D NAND Flash architectures ever proposed, each one owns its merits and demerits. After systematic comparison, it is found that the Vertical Gate (VG) type 3D NAND architecture possesses the superiority of smaller cell size than that of Vertical Channel (VC) one. Besides, the sensing current of this architecture will not be degraded when stacking more layers vertically. Therefore, this work analyzes and optimizes the special effects encountered inherently in the VG-type 3D NAND architecture. In Chapter 2, the VG-type 3D NAND array design and structure will be introduced. Furthermore, the corresponding operations and the decoding methods are also revealed in Chapter 2.
As to Chapter 3, the “split-page” architecture that previously proposed by Chen et al., will be reviewed and its array efficiency will be discussed. Then we will propose a new string decoding scheme, named stagger string select line (stagger SSL) scheme, to improve the array efficiency from 71% to 81%. The corresponding operations and electrical data of this scheme will also be studied therein. Stagger SSL scheme is a promising method for cost-effective design of VG-type 3D NAND architecture in the future.
In 3D NAND process, the process capability of the critical etching module is limited by the highest aspect ratio (AR) that could be achieved by the etching tool. Thus, for a given stack height, we will obtain a higher array capacity by scaling down the thickness of each memory layer. In Chapter 4, the Z-pitch (one poly-silicon and one oxide) reduced from 60nm to 18nm were successfully demonstrated by using two-layer devices. However, the memory margin and read current are degraded accordingly when shrinking the Z-pitch. As to the mechanisms of memory margin degradation, both “Z-interference” and “Z-disturbance” are introduced to explain the Vt (threshold voltage) shift of inhibited transistor. Among them, Z-interference is the major killer of memory margin. Hence, the Z-interference is analyzed in detail in Chapter 5 by eight-layer devices. Aided by simulation verification, the experimental data are analyzed to propose a suitable Z-pitch as the baseline for fabricating VG-type 3D NAND. In addition, several approaches are discussed to suppress the Z-interference and enlarge the memory margin.
Not only the Z-pitch factor but also the horizontal distances can directly affect the device performances. Among various horizontal distances, one important parameter is the distance between edge word line (WL) and ground select line (GSL) or string select line (SSL) transistors. In Chapter 6, the distance effect on VG-type 3D NAND array operations, including read current, erase speed, and programming inhibition performance are discussed. Based on experimental and simulation data, the suitable distance will be summarized as a design guideline in the end of Chapter 6.
Finally, we will conclude the results from Chapters 3 to 6 to provide important guidelines on the perspectives of fabrication aspect and design aspect. Through these studies, we can well understand its merits and limitations of VG-type 3D NAND architecture.

並列關鍵字

3D structure ； Flash memory ； Semiconductor technology ； TFT transistor ； Charge-trapping device

參考文獻

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