無線測試系統模型與雛形之建構

Modeling and Prototyping the Wireless Test System

張天與(Tien-Yu Chang)

指導教授 ： 黃稚存

國立清華大學/電機資訊學院/資訊工程學系/碩士(2008年)

摘要

隨著製程不斷演進，積體電路(IC)的設計複雜度和工作速度也越來越高，也使得測試的成本不斷增加。高階的測試機台因為高測試準確度的要求，而變得非常昂貴。為了解決高測試成本的問題，許多新的測試方法，例如: 內嵌式DFT (design- for-test) 模組的測試機台，開放式架構的測試機台，都被拿來處理這些問題。但在這些方法下，傳統測試的限制依舊存在於這些架構下。近年來，無線測試的概念已逐步被提出，和傳統接觸式的測試方法比較，整體的測試成本是可以大量的被減少的。
在此篇論文內，我們展示了一個36x36組的無線測試系統雛型，整合了改良後的測試通訊協定模組之晶片。此外，一個較小，可攜帶式，整合了多種不同測試核心的系統雛型，也被提出。藉由系統雛型的實作，我們將整合性的通訊模組與測試模組整合成單一的測試核心(device under test)，包括了記憶體(memory)，記憶體自我測試電路(memory-BIST)，無線通訊模組，內嵌式無線收發器，和多重測試時脈訊號產生器。此測試核心已被整合完成並下線。
藉由實作上所得到的系統特性，我們架構了一個針對下一代多重待測端的無線測試通訊協定的系統階層模型。不同的測試核心，如記憶體自我測試，邏輯掃描測試，都在此模型上分析並評估對於此多重待測端通訊協定之效能及影響。藉由系統層級的模擬，系統效能的瓶頸可被分析與找出。我們提出了一個將測試資料比對移往帶測端電路的方法，可有效減輕系統瓶頸的負擔。此系統模可大量且有效的去分析觀察測試系統在不同的參數運作下，測試校能與成本中的相對關係。

關鍵字

晶圓無線測試 ； 無線測試協定 ； 晶圓測試架構 ； 晶圓測試介面

並列摘要

As the process technology enters the deep sub-micron era, the test cost of the semiconductor keeps increasing due to the more and more complicated functions in an integrated circuit, with higher and higher operating speed. High-end tester is expensive because of its higher test accuracy. Many technologies, e.g., DFT (design-for-test) tester with embedded test features and open-architecture tester, have been investigated to cope with these urgent testing issues. However, the limitations in these traditional ATEs (automatic test equipments) still exist.
Recently, the concept of the wireless test system have been developed. Comparing with the traditional test methodology with contacted probing, the overall test cost can be reduced dramatically.

In this thesis, we present a 36x36 prototype of the wireless test system, with improved communication protocol and circuitry. In addition, a mobile version has also been implemented, supporting heterogeneous core tests. With the experiences of the working prototypes, we also cooperate with others to integrate our communication components into a single device under test (DUT), including the memory cores under test, memory built-in self-test (MBIST), wireless test wrapper, data exchange unit (DEU), media access control (MAC) unit, baseband unit, wireless receiver, transmitter, and multi-clock generator.
The test chip has been implemented and fabricated.

Based on the physical characteristics of the implementations, a system-level model of the next-generation multicast wireless test protocol has been constructed. Several core test technologies, such as MBIST, logic scan (LSCAN), and UMC-SCAN (universal multicast scan) have been evaluated and analyzed using our system-level simulation. With our system-level simulation, system bottleneck can be identified and alleviated by the proposed test approach to validate the test responses with the golden ones inside the wireless test wrapper. The rapid design exploration of our wireless test system makes the trade-off between the test performance and cost very efficiently.

並列關鍵字

Wafer-Level Wireless Testing ； Wireless Test Protocol ； Wafer-Level Test Architecture ； Wafer-Level Test Interface

參考文獻

[1] Yueh-Chih Hsu, “Design and implementation of the wireless test protocol and interface”, Master Thesis, Dept. Computer Science, National Tsing Hua University, Hsinchu, Taiwan, July 2007.

[5] P.-K. Chen, Y.-T. Hsing, and C.-W. Wu, “On feasibility of HOY—a wireless test methodology for VLSI chips and wafers”, in Proc. Int’l Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006.

[6] Chun-Kai Hsu, “Area and test cost reduction for hoy wireless test system using system level design techniques”, Master Thesis, Dept. Electrical Engineering , National Tsing Hua University, Hsinchu, Taiwan, July 2008.

[8] L.-M Deng and C.-W Wu, “A hybrid bist scheme for multiple heterogeneous embedded memories”, in 16th IEEE Asian Test Symp. (ATS), Beijing, China, 2007.

[10] Chieh-Ming Chang, “Design and implementation of a baseband transceiver for hoy wireless test platform”, Master Thesis, Dept. Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, July 2007.