應用於互補式金屬氧化物半導體影像感測器以毗連像素傳遞技術讀出之時間延遲積分電路架構

這篇論文提出了一應用於互補式金屬氧化物半導體影像感測器(CIS)時間延遲積分(TDI)電路架構，其架構以毗連像素傳遞技術(APST)讀出。藉由毗連像素傳遞技術讀出方式，不需要增加多餘像素內元件以及金屬繞線，來實現一個仿電荷耦合元件(CCD)的時間延遲積分功能。憑藉像素外的同行共用單位增益緩衝器，像素內的影像訊號有效地被傳遞至相鄰的像素並且累加。此論文所提出的時間延遲積分電路架構擁有許多特色。首先，由於用作傳遞及讀出訊號的同行共用單位增益緩衝器，功率消耗和面積因此大為減少。其二，此論文所提出的時間延遲積分電路架構擁有像電荷耦合元件簡單傳遞以及累加訊號的優點，且其像素為一個基本的三個電晶體的主動像素感測器。主要兩顆chip已被設計且提出為了彼此比較並且驗證TDI的功能。陣列為128x6 且像素大小為6x6μm2 及23.1%填充係數的APST時間延遲積分電路使用TSMC 0.18μm 1P6M CIS 技術設計並且完成晶片研製，此晶片擁有實現6個時間延遲積分級數。在3.3V的工作電壓下，其量測結果成功驗證了時間延遲積分的功能與效能。藉由6個時間延遲積分階數增進了7dB SNR，5.2% 光響非均勻性，功率損耗僅為4.43uW/column，以上特性皆表示其電路為有效應用於遙測感測器。本論文採用同行共用單位增益緩衝器，使晶片面積僅為 1.7mm x 1.3mm，並且傳輸效率改善高達至99.6%。陣列為128x16 且像素大小為6x6μm2 及23.1%填充係數的revised APST時間延遲積分電路使用TSMC 0.18μm 1P6M CIS 技術設計並且完成晶片研製，此晶片擁有實現16個時間延遲積分級數。在3.3V的工作電壓下，其量測結果成功驗證了時間延遲積分的功能與效能。藉由16個時間延遲積分階數增進了13dB SNR，5.9% 光響非均勻性，功率損耗僅為4.89uW/column。本論文採用同行共用單位增益緩衝器，使晶片面積僅為 1.7mm x 1.3mm。

關鍵字

時間延遲積分；毗連像素傳遞技術；互補式金屬氧化物半導體影像感測器

並列摘要

In the thesis, a time delay and integration (TDI) structure for CMOS image sensor (CIS) with adjacent pixel signal transfer (APST) is presented. The CCD-like TDI function is achieved in CIS by proposed APST without additional in-pixel device and routing effort. The in-pixel integrated signal is transferred to adjacent pixel and summed up by an off-pixel column-shared unity-gain buffer. There are several features of the proposed TDI structure. First, due to the column-shared unity-gain buffer utilized to transfer and readout signal, the power consumption and area occupancy are reduced and minimized greatly. Second, the proposed circuit has the advantage of CCD such as the ease of the summing signals with basic 3T APS pixel. There are proposed chips which are designed to compare and verify TDI function. A 128x6 APST TDI sensor with 6x6μm2 pixel size has been designed and fabricated in TSMC0.18μm 1P6M CIS technology providing 6 TDI stages with fill factor of 23.1%. The TDI function and the superior performance have been verified by experimental measurement with 3.3V power supply. It achieves a SNR improvement of 7dB with 6 TDI stages, a PRNU of 5.2%, and a low power consumption of 4.43uW/column which provides an optimized solution for remote sensing. Thanks to the column-shared op-amp adopted in this thesis, the chip size is minimized to 1.7mm x 1.3mm, and the transfer efficiency is also improved up to 99.6%. A 128x16 revised APST TDI sensor with 6x6μm2 pixel size has been designed and fabricated in TSMC0.18μm 1P6M CIS technology providing 16 TDI stages. The TDI function and the superior performance have been verified by experimental measurement with 3.3V power supply. It achieves a SNR improvement of 13dB with 16 TDI stages, a PRNU of 5.9%, and a low power consumption of 4.89uW/column. Thanks to the column-shared op-amp adopted in this thesis, the chip size is minimized to 1.7mm x 1.3mm.

並列關鍵字

time-delay integration ； Adjacent Pixel Signal Transfer ； CMOS image sensor

參考文獻

[1] G. Lepage, J. Bogaerts, G. Meynants, “Time-Delay-Integration Architectures in CMOS Image Sensors,” IEEE Trans. Electron Devices, Nov. 2009,vol. 56, pp. 2524-2533.

[3] Melik Yazici, Huseyin Kayahan, Omer Ceylan, and Yasar Gurbuz, “Design of a ROIC for Scanning Type HgCdTe LWIR Focal Plane Arrays,” in Proc. Electron. Imag. Conf., 2010, vol. 7660, 76603X

[4] G. Lepage, D. Dantès, and W. Diels, “CMOS long linear array for space application,” in Proc. Electron. Imag. Conf., Jan. 2006,vol. 6068, pp. 61–68.

[5] Chul Bum Kim, Byung-Hyuk Kim, Yong Soo Lee, Han Jung, Hee Chul Lee, “Smart CMOS Charge Transfer Readout Circuit for Time Delay and Integration Arrays,” in Proc. IEEE Custom Integr. Circuits Conf., 2006, pp.651-654.

[6] H.-S. Wong, Y. L. Yao, and E. S. Schlig, “TDI charge-coupled devices: Design and applications,” IBM J. Res. Develop. 1992, vol. 36, no. 1, pp. 83–105, Jan..

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應用於互補式金屬氧化物半導體影像感測器以毗連像素傳遞技術讀出之時間延遲積分電路架構

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