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  • 學位論文

應用於後互補式金屬氧化物半導體之低功率高介電係數/三五族金屬氧化物半導體元件閘極金屬堆疊之研究

INVESTIGATION OF METAL GATE STACK FOR POST CMOS LOW POWER HIGH-K/III-V MOS DEVICES APPLICATIONS

指導教授 : 張翼教授

摘要


摘要 為因應未來互補式金屬氧化物半導體元件低功耗的需求,開發適用於邏輯應用的新型金屬/高介電質/三五族(III-V)材料結構為當前重要的研究課題;因此,本論文研究應用在砷化銦鎵(InGaAs)金屬氧化物半導體(MOS)元件之新型金屬閘極疊層與高介電質層,研究內容包含新型閘極電極金屬合金的製造以及改善二氧化鉿(HfO2)氧化層在砷化銦鎵金屬氧化物半導體元件上之介電係數,共可區分為五大研究方向。 首先,由於平帶電壓(VFB)是影響金屬功函數的重要參數,亦會影響金氧半元件臨界電壓(VT)的預測,因此,本研究提出一個適用於n型砷化銦鎵金氧半元件結構的平帶電壓的預測方法;此研究中,我們也探討氧化物/半導體界面處的電容電壓滯後和界面缺陷密度對取得精確的平帶電壓值的影響;其結果也適用於其他具有高遷移率通道材料之金氧半元件。 研究二,本論文研究以氮化鋁(AlN)作為二氧化鉿與砷化銦鎵通道之鈍化層,探討其金屬功函數(WF)以及在其閘極結構堆疊下的能帶圖,我們發現加入氮化鋁鈍化層將使得二氧化鉿與基板間減少了偶極0.18電子伏特,與從電容-電壓特性所得到的偶極值以及X射線光電子能譜(XPS)測量的結果一致;並發現在真空下鎳(Ni)的有效功函數(EWF)為5.55電子伏特比鎳金屬的功函數還大,而二氧化鉿和氮化鋁/砷化銦鎵的價電帶與導電帶的偏移分別為,2.82電子伏特以及2.06電子伏特。 研究三,為了實現互補式金屬氧化物半導體元件之低功率損耗低,本論文更進一步的研究出適用在二氧化鉿/砷化銦鎵金屬氧化半導體元件之多層鈦鎳(TiNi)合金閘極金屬;由於為使元件具低損耗,閘極金屬有效功函數必須與通道材料能帶邊界互相對齊,並具有小的功函數的變化(WFV);而此鈦鎳合金閘極金屬之研究發現鈦鎳在熱退火後,鎳原子擴散至鈦層中,其有效金屬功函數從4.41電子伏特增加至4.62電子伏特,而鈦鎳合金直到600℃熱退火前還是保持為非晶狀態及小功函數變化;與鈦及鈦純金屬相比,由於使用鈦鎳合金將使其金屬與氧化層界面會形成TiOxNi介面層,以防止鎳原子擴散至二氧化鉿中並降低鈦與二氧化鉿反應,因此鈦鎳合金更適於元件之閘極金屬。 研究四,研究開發了鉬(Mo)/鈦/二氧化鉿結構之砷化銦鎵通道金屬氧化物半導體電容器(MOSCAP),研究發現在鉬與二氧化鉿間摻雜鈦後,二氧化鉿的介電係數從將從17(未摻雜鈦)增加到25(摻雜鈦),增加了47%,且亦不影響二氧化鉿/砷化銦鎵金屬氧化物半導體電容器的界面陷阱密度;由於金屬氧化物半導體電容器在強反轉時具有低洩漏電流,而具有鈦摻雜的元件在調整砷化銦鎵費米能階時所需的閘極電極能帶彎曲量是未有鈦摻雜元件的一半,這驗證了利用有鈦摻雜的二氧化鉿元件可以減少金屬氧化物半導體場效電晶體操作時的能量損耗;此外,在鈦摻雜的高介電常數二氧化鉿的鉬/鈦效功函數很靠近砷化銦鎵導電帶,因此,此摻雜鈦的元件製作方式非常適合應用於n型金屬氧化物半導體元件。 最後,研究探討鉬、鎳與鈀(Pd)閘極金屬與二氧化鉿之介面間的退化問題,研究結果發現位於鈀與二氧化鉿的介面存在著不穩定的氧化鈀,而此鈀-氧鍵的低離解能(Ds)將會導致鈀/二氧化鉿/砷化銦鎵電容器中在鈀/二氧化鉿界面處的氧分離;此外,使用鈀閘極金屬時,在元件熱退火過程中亦將產生氧離子與氫氧根離子,使得氧化鈀層更加不穩定; 而在鉬、鎳/二氧化鉿/砷化銦鎵電容器並沒有發現上述問題,因此,相較於鈀,鉬與鎳更適合用於未來金屬氧化物半導體場效電晶體之閘極金屬。

並列摘要


Abstract The requirement of low power consumption of future complement metal oxide semiconductor (CMOS) leads to the deep studies of the metal/high-k/III-V structure applicable for the logic applications. This dissertation aims to study the metal gate stack for In0.53Ga0.47As MOS devices. It includes in the fabrication of metal alloys acted as a gate electrode and the improvement of the permittivity of HfO2 acted as oxide layer for In0.53Ga0.47As MOS devices. Firstly, a modified method to accurately determine the flat band voltage (VFB) of the In0.53Ga0.47As n-type MOS device is constructed. Flat band voltage has an important role in extracting the effective work function of metal, and it will affect the prediction of the threshold voltage of the MOS devices. The effects of capacitance voltage hysteresis and interface trap density at the oxide/semiconductor interface on the accuracy of the extracted VFB values are discussed. The results are also applicable to other MOS devices with high mobility channel materials. Secondly, the effects of AlN passivation layer between the HfO2 and InGaAs channel on both the metal work function (WF) and band alignment of the gate stack were investigated. We found that the AlN layer induces a dipole  = 0.18 eV between HfO2 and substrate. The dipole value obtained from capacitance-voltage characteristics performs a good agreement with the results of X-ray photoelectron spectroscopic measurements. The effective work function of Ni is found to be 5.55 eV which is larger than its WF in vacuum. The valance band offset and the conduction band offset of HfO2 with AlN/In0.53Ga0.47As are found to be 2.82 eV, and 2.06 eV, respectively. Thirdly, the multilayer TiNi alloys were fabricated to apply as the gate metals for HfO2/In0.53Ga0.47As MOS devices. To achieve low power consumption for CMOS devices, the gate metals must have effective work function (EWF) aligned with the band edges of the channel material and have a small work function variation (WFV). It is found that the EWF of TiNi alloys increases from 4.41eV for as-deposited sample to 4.62eV after the alloy was annealed due to the diffusion of Ni atoms into Ti layer. The multilayer TiNi alloy remained amorphous-phase with small WFV until annealed at 600oC. The TiNi alloy is thermally more stable as compared to either Ti or Ni metal because the TiOxNi interfacial layer prevents the diffusion of Ni atoms into HfO2 film and the further reaction of Ti with HfO2. Fourthly, we report the Mo/Ti/HfO2(Ti) metal/dielectric stack fabricated on InGaAs channel metal oxide semiconductor capacitors (MOSCAPs). The dielectric constant of HfO2 was found to increase 47% from 17 (for un-doped sample) to 25 (for Ti doped sample) without increasing the interface trap density of the HfO2/InGaAs MOSCAPs. A strong inversion behavior with low leakage current for the MOSCAP was observed. The band bending in the gate electrode needed for tuning the InGaAs Fermi level for the sample with Ti doped HfO2 is less than half of the sample with un-doped HfO2, suggesting the reduction of the power consumption of the metal oxide semiconductor field effect transistor (MOSFET) device using the Ti doped HfO2. The high dielectric constant of Ti doped HfO2 with the effective work function of Mo/Ti on HfO2 near the conduction band edge of InGaAs is ideal for the application for the NMOS devices. Finally, the degeneration of the metal/HfO2 interfaces for Mo, Ni, and Pd gate metals were studied. It was found that an unstable PdOx interfacial layer at the Pd/HfO2 interface induced the oxygen segregation for the Pd/HfO2/InGaAs metal oxide capacitor (MOSCAP). The low dissociation energy (Ds) for the Pd-O bond attributed to the oxygen segregation at the Pd/HfO2 interface. The PdOx layer is unstable and contains O2 and OH ions which are movable during annealing and electrical stress test. The phenomenon was not observed for the (Mo, Ni)/HfO2/InGaAs MOSCAPs. The results provide the guidance for choosing the proper metal electrode for the MOSFET.

參考文獻


[1] G. E. Moore, "Cramming More Components Onto Integrated Circuits," Proceedings of the IEEE, vol. 86, pp. 82-85, 1998.
[3] J. A. D. Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi, and X. Zhao, "Nanometer-Scale III-V MOSFETs," IEEE Journal of the Electron Devices Society, vol. 4, pp. 205-214, 2016.
[4] K. Schuegraf, M. C. Abraham, A. Brand, M. Naik, and R. Thakur, "Semiconductor Logic Technology Innovation to Achieve Sub-10 nm Manufacturing," IEEE Journal of the Electron Devices Society, vol. 1, pp. 66-75, 2013.
[5] G. He, Z. Sun, M. Liu, and L. Zhang, "Scaling and Limitation of Si-Based CMOS," in High-k Gate Dielectrics for CMOS Technology, ed: Wiley-VCH Verlag GmbH & Co. KGaA, 2012, pp. 1-29.
[6] R. Pillarisetty, "Academic and industry research progress in germanium nanodevices," Nature, vol. 479, pp. 324-328, 2011.

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