以氮化矽/矽奈米點/氮化矽為儲存層的奈米線複晶矽薄膜電晶體非揮發性記憶體之研究

A Study on the Nanowires Poly-Si TFT Nonvolatile Memory with Si3N4/Si-Nanocrystal/ Si3N4 Hybrid Trap Layer

蔣季宏(Ji-Hong Chiang)

指導教授 ： 吳永俊

國立清華大學/原子科學院/工程與系統科學系/碩士(2009年)

摘要

Nonvolatile flash memory is very popular for portable electronics, and the demand for memory density multiplies every year. Although flash memory is aggressively scaled for high-density applications, continuing to scale according to Moore’s law is becoming increasingly difficult because of both process and device limitations. This three-dimensional (3D) multi-layer-stack memory that is based on poly-Si TFTs can be a good solution for ultra-high-density memory. SONOS-type NVM with hybrid Si3N4/Si-NC/ Si3N4 trap layer can improve the retention and endurance Hence, we first investigate NWs TFT NVM using Si3N4/Si-NC/Si3N4 hybrid trap layer with excellent performance and COMS compatible process for future 3D stack NVM application.
This work demonstrates a Nanowires (NWs) poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory (NVM) that utilizes Si3N4/Si-nanocrystal (Si-NC)/Si3N4 hybrid trap layer for 3D Flash memory. The NWs poly-Si TFT NVM has high program/erase (P/E) efficiency and large memory window due to its superior gate control. Utilizing Si3N4/Si-NC/Si3N4 hybrid discrete trap layer, the NVM exhibits excellent high–temperature (150oC) retention (>108 for 6% charge loss), up to 104 P/E cycles, and two-bit operation due to its discrete trap and quantum confinement effect.

關鍵字

非揮發性記憶體 ； 奈米線 ； 複晶矽薄膜電晶體 ； 矽奈米點

並列摘要

無資料

並列關鍵字

Nonvolatile Memory ； Nanowires ； Poly-Si TFT ； Si-Nanocrystal

參考文獻

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