標準CMOS製程之薄膜殘餘應力萃取

Residual Stress Extraction Based on CMOS Standard Process

劉育智(Yu-Chih Liu)

指導教授 ： 方維倫

國立清華大學/工學院/動力機械工程學系/碩士(2009年)

https://doi.org/10.6843/NTHU.2009.00542

摘要

本研究是依據現今晶圓製造廠之CMOS標準製程設計並且製造出符合CMOS標準製程規範之不同薄膜堆疊微懸臂樑做為測試結構，當這些測試結構被懸浮後，由於不同膜層間殘餘應力大小有所差異會造成微懸臂樑有出平面方向的形變產生，藉由對這些不同薄膜堆疊的微懸臂樑做量測，可以初步對於不同薄膜堆疊造成測試結構的出平面形變有所了解，除此之外，亦可藉由對所設計之測試結構做分析，即可萃取出CMOS標準製程中每層薄膜之殘餘應力值。然而，不同薄膜堆疊的微懸臂樑各層薄膜之間的殘餘應力場相互作用，分佈複雜，難以藉由多層薄膜堆疊的微懸臂樑解出其中單一薄膜的殘餘應力值，因而本研究也與晶圓製造廠合作，製作CMOS標準製程中單一膜層之測試結構，並利用較易萃取出機械性質的單一薄膜結構做為分析多層堆疊微懸臂樑時的參考。而後提出萃取多層薄膜堆疊微懸臂樑殘餘應力之方法與驗證其可行性。希望藉由這些測試結構分析計算出CMOS標準製程中薄膜之殘餘應力，以提供往後欲使用此CMOS標準製程之使用者模擬設計時參考。

關鍵字

CMOS標準製程 ； 薄膜殘餘應力

並列摘要

Recently, using CMOS(complementary metal oxide semiconductor) standard process fabricates MEMS (Micro-electromechanical System) device has been popularly. Integrating CMOS with MEMS can reduce the area of device, batch production and decrease the cost of production. However, the residual stress of thin film caused structure unpredictable deformation. Therefore, it is necessary to know residual stress of CMOS standard process thin film for designer.
This study design a number of cantilever structures according to CMOS design rules. These cantilever structures are deposited by different thin film. The residual stress of thin film caused the cantilever structures out-of-plane deformation. According to appropriate analytical method, the curvature of each cantilever structures can be predicted and the residual stress of CMOS standard process thin film can be extracted. Eventually, we can build up database of CMOS standard process thin film residual stress. The database can provides reference for designer that want to use CMOS standard process.

並列關鍵字

CMOS standard process ； thin film residual stress

參考文獻

[2] J.A. Thorton, and D.W. Hoffman, “Stress Related Effects in Thin Films,” Thin Solid Films, 171, pp 5, 1989.

[3] H. Miyajima, and M. Mehregany, “High-Aspect-Ratio Photolithography for MEMS Applications,” Journal of Microelectromechanical Systems, 4, pp 220-229, 1995.

[4] H. Xie, L. Erdmann, X. Zhu, K.J. Gabriel, and G.K. Fedder, “Post-CMOS Processing for High-Aspect-Ratio Integrated Silicon Microstructures,” Journal of Microelectromechanical systems, 11, pp 93-101, 2002.

[5] J.S. Pulskamp, A. Wickenden, R. Polcawich, B. Piekarski, M. Dubey, and G. Smith, “Mitigation of residual film stress deformation in multilayer microelectromechanical systems cantilever devices,” Journal of Vacuum Science and Technology B, 21, pp 2482-2486, 2003.

[7] Y.-J. Huang, T.-L. Chang, H.-P. Chou, “Study of symmetric microstructures for CMOS multilayer residual stress.” Sensors and Actuators A: Physical, 150, pp 237-242, 2009.