Variability and Reliability Aware Performance & Timing Optimization of VLSI Designs

考慮變動及可靠度之大型積體電路效能及時序最佳化

蘇祐世(Yu-Shih Su)

指導教授 ： 張世杰

國立清華大學/電機資訊學院/資訊工程學系/博士(2009年)

摘要

在先進製程 (90nm)技術下，變動性(variability)—如製程、電壓、和溫度變化(PVT variation)以及設計中多種不同運作模式和限制，已經是造成晶片設計發生錯誤的重要原因。由於製程、電壓、和溫度變化所造成的時序(timing)不確定，會造成晶片設計不符合所要求的時序規格(timing specification)。並且，要設計出一個唯一的晶片佈局(Layout)來同時符合先進設計中所存在的多種運作模式下的眾多設計限制，非常的困難。
在本論文中，我們主要提出三個方法，在考慮變動性下，對晶片設計的可靠性和時序做最佳化。首先，我們提出一個可偵測時序錯誤的架構(TED)來偵測並修復因為製程、電壓、和溫度變化所造成的時序錯誤(timing error)。我們的架構可以藉由容忍時序變化(timing variation)的特性來增加設計上的可靠度，並且不會有之前相關架構所存在的短路徑(short path)問題。
接著，傳統上設計時序的最佳化，通常考慮設計中可能發生的最糟情況(worst-case)。但是這些最糟情況在運作中非常少發生，這導致傳統最佳化的方法在資源運用上並不有效。在本論文中，我們跟據可變動時脈設計(variable latency design)的方式，提出一個再次和成(re-synthesis)的方法來增加設計的效能。
最後，考慮複雜設計架構下的多個運作模式，建立一個唯一的時鐘架構(clock network)滿足所有運作模式下的限制非常困難。我們提出一個在原本時鐘架構中，插入可調變延遲裝置(adjustable delay buffer)的方式，藉由在不同運作模式下調整各可調變延遲裝置的延遲時間，來使得此時鐘架構可以同時滿足多個運作模式下的時鐘偏移限制(clock skew constraint)。我們提出一個決定各可調變延遲裝置延遲時間(delay assignment)的線性時間最佳化演算法，使得此時鐘架構在各運作模式下的時鐘偏移為最小。

關鍵字

Variability ； VLSI ； Performance

並列摘要

Under 90nm technologies, variability, such as PVT variation and multiple design modes/corners, have become one of leading causes for chip failures. The delay uncertainty raised by PVT variation may cause a design to fail its’ timing specification. In addition, it has becomes tremendously difficult to create a single layout that satisfies numerous constraints imposed by the multiple modes of operations. In this thesis, we propose three mechanisms for reliability and timing optimization considering variability. We first propose an error-detecting architecture (TED) to detect and correct timing errors caused by PVT variation. This TED architecture can tolerate delay variation and enhance timing reliability without the short path problem in previous works. Second, the traditionally strategy of optimizing a circuit for the rarely activated worst-cases conditions could lead to inefficient resource use. We propose a re-synthesis method based on variable-latency design style to improve design performance. Finally, considering multiple design modes, building a single clock network to satisfy all constraints in each mode is difficult. We insert adjustable delay buffers (ADB) whose delay can be tuned in each mode into clock tree to simultaneously satisfy multiple clock skew constraints. We propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all assignments. In addition, to obtain the accurate probability information of rare activation, we also propose an efficient approach to find the timing distribution of a circuit.

參考文獻

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