系統單晶片下考量電壓島佈局的平面規劃

採用多種工作電壓（multiple-supply voltages）在單晶片系統（System-on-Chip）的設計上是一條實現低功率的有效途徑。實體設計（physical design）流程中，在平面規劃（floorplanning）階段考量多種工作電壓的問題是最適當的。過去有許多方法將此問題分成設定工作電壓（voltage assignment）的問題以及平面規劃的問題。這篇論文中，我們提出了一個利用模擬退火法（simulated annealing）來考量電壓島（voltage island）佈局的平面規劃，以同時解決這兩個問題。我們的方法使用可以有效率地在模擬退火時評估電源耗費的 Corner Block List [1] 作為平面規劃的表示法。實驗結果顯示，我們的演算法可在一個平面規劃中產生平均約三個電壓島，並減少 31.63% 的電力消耗。與過去的方法 [2] 相比，我們的方法可以得到較少的閒置空間（deadspace）、總線長（total wirelength）、電源消耗以及電位移轉器（level shifter）的數量。

關鍵字

實體設計；平面規劃；多重工作電壓；電壓島

並列摘要

Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for applying MSV's design. Previous works have addressed the MSV's design problem at floorplanning stage by solving the voltage assignment problem and the floorplanning problem separately. In this thesis, we propose a simulated annealing (SA) based voltage island-aware floorplanning algorithm to solve the two problems simultaneously. Our algorithm is based on corner block list [1] which is efficient for integrating the evaluation process of power costs function into SA. Experimental results show that our algorithm could save 31.63\% total power consumption by forming three voltage islands in average. We could obtain better deadspace, total wirelength and power consumption than the previous work [2] as well.

並列關鍵字

physical design ； floorplanning ； multiple-supply voltages ； voltage island

參考文獻

[1] X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu, “Corner block list: an effective and efficient topological representation of non-slicing floorplan,” in IC-CAD ’00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, pp. 8–12, 2000.

[3] G. E. Moore, Cramming more components onto integrated circuits. Electronics, 1965.

[4] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, vol. 220. Science, 1983.

[11] J.-M. Lin and Y.-W. Chang, “TCG: a transitive closure graph-based representation for non-slicing floorplans,” in DAC ’01: Proceedings of the 38th conference on Design automation, pp. 764–769, 2001.

[12] P.-N. Guo, C.-K. Cheng, and T. Yoshimura, “An O-tree representation of non-slicing floorplan and its applications,” in DAC ’99: Proceedings of the 36th ACM/IEEE conference on Design automation, pp. 268–273, 1999.

國際替代計量

系統單晶片下考量電壓島佈局的平面規劃

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