A Low-Power Hardware Design for H.264/AVC Baseline Decoder

針對H.264/AVC 基礎規範視訊的低功耗硬體設計

蔡佳達(Chia-Ta Tsai)

指導教授 ： 鍾葉青

國立清華大學/電機資訊學院/資訊工程學系/碩士(2009年)

摘要

H.264/AVC 是由國際標準組織 (ISO)和國際電信聯盟 (ITU)所共同制定的，為目前最新的視訊編碼標準。相較於先前的視訊編碼標準，H.264/AVC提供近二倍的壓縮效率，但是複雜的運算也造成 H.264/AVC很難做到即時處理。其中可變長度解碼 (CAVLD)是解碼器最先處理的部分，因可變長度解碼的循序處理特性，其效能將會影響整個解碼器的效能。此外，在幀內/幀間預測 (intra/inter prediction)時，大量參考像素的讀取及運算是相當耗電的，不利於手持裝置使用 H.264/AVC視訊編碼標準。本論文所提出的可變長度解碼器利用領導零的個數 (NumLZ)和剩餘位元 (TBits)這二個特性來加速查表的過程，並且透過合併係數標誌 (CoeffToken)和號 (SIGN)這二個階段達到每個時脈周期 (clock cycle)可以解碼出一個以上的語法元素 (syntax element)，再加上時脈閘控 (clock gating)可以減少功耗36%。另外，在幀內/幀間預測器的部分，則使用暫存器來暫存已讀取參考像素和預測結果，對於幀內預測可減少參考像素讀取82%和功耗7%；對於幀間預測可減少參考像素讀取66%和功耗12%。 關

關鍵字

H.264/AVC ； 可變長度解碼 ； 幀內/幀間預測 ； 低功耗 ； 基礎規範解碼器

並列摘要

H.264/AVC is the latest video coding standard jointly developed by ITU-T VCEG and ISO/IEC MEPG. H.264/AVC enhances almost two times coding efficiency than prior video coding standards, but the high computational complexity makes it difficult to decode video in real-time even using high-end central process unit. Sequential CAVLD process is the bottleneck of performance, and mass reference pixel access and high computational complex of intra/inter prediction consume a lot of power. The proposed CAVLD uses the prosperities of codeword, numLZ and TBits, to speed up the table lookup process and decodes more than one syntax element by combining CoeffToken and SIGN stage. Besides, the CAVLD reduces at most 36% power consumption after applying the clock gating to shut down some functional blocks when they are unnecessary. Temp registers are used in the proposed intra/inter predictor to keep the accessed reference pixels and prediction result, and 82% reference pixel access is reduced and at most 7% power dissipation is saved in intra prediction and 66% reference pixels access is reduced and at most 12% power dissipation is saved in inter prediction.

並列關鍵字

H.264/AVC ； CAVLD ； Intra/Inter prediction ； low power ； baseline decoder

參考文獻

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