Real-Time Embedded Debug and Trace Platform for System-on-Chip

應用於系統晶片之即時內嵌式偵錯追蹤平台

顏廣愷(Guang-Kai Yen)

指導教授 ： 黃稚存

國立清華大學/電機資訊學院/資訊工程學系/碩士(2009年)

摘要

隨著系統晶片的製程進步，系統晶片的驗證及除錯也越來越困難，尤其當系統晶片裡有多個需要驗證及除錯的目標，或是系統晶片有者不同形式的匯流排，都會增加在系統晶片上驗證及除錯的困難。此外，要如何在系統晶片運行時，能即時的除錯及追蹤，並將追蹤資料記錄下來，也是所要面對的難題之一。

在這篇論文裡，我們提出一個應用於系統晶片的及時內嵌式偵錯追蹤平台。此平台包含了核心監視器(Core Monitor)和匯流排監視器(Bus Monitor)，用來蒐集和壓縮我們所追蹤的核心及匯流排的資料。這個平台使用的四階層的平行硬體架構，來壓縮資料，並用獨立的匯流排來傳送資料，不影響到系統晶片的行為。此平台也包含了Cross Trigger，讓不同的監視器可以去觸發其他的監視器，讓使用者可以去設定比較複雜的追蹤條件，來達到更好的除錯效果。

另外，為了達到減少追蹤資料的效果，我們針對不同的追蹤資料設計了不同的壓縮演算法。在Starfish這是多媒體平台上，我們總共減少了90%的核心追蹤資料及80%的匯流排追蹤資料。我們也提出了將此除錯追蹤平台的硬體面積最佳化的方法。以實作在Starfish為例，我們的除錯偵錯平台只佔了8%的硬體面積。

關鍵字

除錯 ； 壓縮

並列摘要

As the improvement of the SoC technology, it is getting more and more difficult to validate
the functionality of SoC, especially for the debugging of multi-core SoC. There are more
challenges of SoC pre-silicon or post-silicon debugging when SoC becomes more complex,
such as how to trace multiple cores and various types of bus with different clock domains
real-time, and how to handle huge amount of trace data from complex SoC cycle by cycle.
In the thesis, we propose a real-time embedded debug and trace platform (Trace Debug
System) for platform-based or core-based SoC. It consists of Core Monitors and Bus Monitors
which can trace the data from target cores and system bus of SoC. Our Trace Debug System
also contains 4-stage real-time architecture to compress and store trace data cycle by cycle.
And there is an independent Debug Bus to transfer all trace data from Monitors to trace
buffer. In that way, our Trace Debug System would not impact the performance of the target
SoC. Our Trace Debug System also can trace the SoC with various types of system bus with
different clock domains. Moreover, we implement the bottleneck-aware Cross Trigger on our
Trace Debug System so that we can trigger Monitors to trace targets when the user-defined
trace event occurs or the target system hangs because of system bottleneck.
In addition, in order to reduce the huge amount of trace data, we classify trace data to
5 types, and select an individual compression methodology for each types of trace data by
analyzing the trace data from Starfish multimedia platform. As a result, we reduce 90% of
trace data from Starfish DSP core, and reduce 80% of trace data from system bus (AHB).
Moreover, we propose a methodology to optimize area cost of our Trace Debug System
in terms of compression ratio (that affects trace depth) and trace capability. For Starfish
platform, the area cost of our Trace Debug System (with one Core Monitor and one Bus
Monitor) costs only 8%. Besides, under the multi-core environment, the comparison shows
that our approach requires 20.82k gates, which is 36% as compared with previous work.

並列關鍵字

Debug ； Trace compression

參考文獻

in In Proc. Design, Automation, and Test in Europe (DATE), 2005

of Debug Standardization Activities”, in Design & Test of Computers, IEEE, Volume

Systems-on-Chips with Multiple Processor Cores” Proc. IEEE Transactions on Computer,

and Trace Interface for the DSP Platform”, in Proc. IEEE/ACM Design Automation

for Real-time Compression of Forward/Backward Traces in a Circular Buffer”, in Proc.