- 學位論文
新型邏輯製程可自動編程差動多次寫入非揮發性記憶體
A New Logic-Compatible Differential Self-Selective Program Multiple-Time Programmable Non-Volatile Memory Cell
摘要
在積體晶片系統的發展上，內嵌式記憶體是不可或缺的重要組成，這種不需額外的製程步驟即可整合到CMOS邏輯製程的非揮發性記憶體也逐漸為大家所重視。緃使許多記憶體技術在該領域被提出且進行競爭，但提供多次可程式設計性的記憶體並不多見。本論文提出一新型邏輯製程N通道差動內嵌式記憶體，此可程式編輯記憶體利用差動結構的設計，可達到自動完成寫入動作，具有完全符合CMOS邏輯製程技術。 此新型邏輯製程可自動編程差動多次寫入非揮發性記憶體利用選擇閘極和源極來控制通道熱離子轟擊引發熱電子注入編程操作方式、與熱電洞注入完成抹除操作，達成可多次編輯功能；其組成可縮小至約三個N型通道金氧半場效電晶體，有效的降低元件面積。此新型記憶胞的編程抹除時間在2毫秒內，元件的耐久度高達10萬次，資料保存性在85℃、120℃、150℃皆通過1000小時的考驗。在差動的架構設計上，此記憶胞提出新型的自我選擇寫入功能，拉大邏輯0與1的可辨別範圍，有效提高資料保存度與可靠度、解決因製程可能產生的不對稱問題並簡化相對應的電路設計。本文所提出之新型自動編程差動記憶體擁有良好的特性，並為全邏輯製程之系統整合晶片提供新的選擇和應用。
並列摘要
During the progression of integrated system on chip, the embedded nonvolatile memory (NVM), which does not need extra masks and to be fabricated by standard complementary metal oxide semiconductor (CMOS) process have been widely studied. Though there are many technologies and designs have been studied and developed for logic NVM applications, but until now, there is not an overall solution which can serve high program and erase performance, thin gate oxide of CMOS logic process constraint, and superior high endurance property with an acceptable cell size. This study proposes a brand-new cell structure and operation method to achieve the above merits with fully CMOS logic compatible technology and processes. The new logic-compatible differential self-selective program multiple-time programmable nonvolatile memory, which is using CHE program and CHH erase by controlling the voltage of SG and BL, the program/erase speed can be achieved within 2msec, and the cell also consists of 3 transistors only. Moreover, the on/off window is successfully risen up to 106 orders post 105 cycling stresses. In terms of reliability characterization, the cell has been verified to pass the criteria after 1000 hours of retention bake at 85℃, 120℃, and 150℃. Finally, the proposed new self-selective program method is able to increase the sensing window twice, to improve the reliability effectively, and to avoid the mismatch problem, further to simplify the circuit design by overhead reduction. The high performance differential-nonvolatile memory cell has been demonstrated and providing a very promising solution in logic NVM application beyond 0.18um nodes.