在后羿平台上以進階交流掃描為基礎的延遲測試與特徵描述

隨著製程不斷的演進，越來越多的因素會造成製程偏移，使得電路中的延遲時間難以預測。再加上電路工作頻率不斷的提升，使得以往不具影響力的小型延遲錯誤，也開始對於電路的運作造成威脅，因此延遲測試在確保晶片品質的角色日益重要。在這篇論文中，我們提出了三個方法來進行延遲測試與特徵描述，並在后羿平台上實做我們所提出的技術。我們提出的第一個方法，提供了更有效率的方式去量測每一個測試向量的最大延遲時間，以對電路進行特徵描述，並可分析該晶片是否有小型延遲錯誤。實驗的結果顯示該方法可以有效的將測試時間減少81.8%。第二個方法是針對量產測試所設計。由於現在普遍採用的實速測試並不能有效的偵測到小型延遲錯誤。而測量每個測試向量的最大延遲時間以偵測小型延遲錯誤的方式又太花費時間，並不適合量產測試。因此我們提出了這個方法，除了可以有效的偵測到小型延遲錯誤，並同時提供有缺陷的晶片快速特徵描述，以幫助我們做進一步的處理。實驗的結果顯示，這個方法可以有效的判斷出哪些具有小型延遲錯誤的晶片，其瑕疵的嚴重性較高，有比較高的機率會在實際使用的時候造成錯誤。第三個方法是藉由進階交流掃描來從一個真實的晶片中粹取出波形。憑藉著后羿平台幾乎沒有限制的測試記憶體，我們可以儲存大量的資料來重建出晶片內部的波形，以幫助我們進行矽晶片偵錯。我們並進一步的在實做出來的晶片上展示該方法。

關鍵字

延遲測試；交流掃描；特徵描敘；小型延遲錯誤

並列摘要

Small delay defects, often escaping from traditional delay testing, could cause a device to function abnormally in the field. Therefore detecting these defects is often necessary in modern delay testing. To address this issue, we propose three test modes in a new methodology called AC+ scan, meaning that the resolution of traditional AC scan test can be enhanced by embedding an All-Digital Phase-Locked Loop (ADPLL) into a circuit under test (CUT). AC+ scan can be executed by a next-generation test platform, HOY platform. The first test mode of our AC+ scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that this method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips will be more likely to cause failure in the field. The third test mode is to extract the waveform of each flip-flop’s output in a real chip. This is made possible by taking advantage of the almost unlimited test memory on HOY test platform, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debug. We have successfully manufactured a Viterbi decoder chip with feature of AC+ scan inside to demonstrate its capability.

並列關鍵字

Delay testing ； characterization ； AC scan ； small delay defect

參考文獻

[1] H. Mahmoodi, S. Mukhopadhyay, K. Roy, “Estimation of Delay Variations due to Random-Dopant Fluctions in Nanoscale CMOS Circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, September 2005, pp. 1787-1796.

[3] P. Nigh, and A. Gattiker “Test Method Evaluation Experiments & Data,” Proc. of International Test Conference, 2000, pp. 454-463.

[7] N. Ahmed, M. Tehranipoor, V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” Proc. of Design Automation Conference, 2006, pp. 320-324.

[9] M. Yilmaz, K. Chakrabarty, M. Tehranipoor, “Test-Pattern Grading and Pattern Selection for Small-Delay Defects,” Proc. of IEEE VLSI Test Symposium, 2008, pp. 233-239.

[11] J.-J. Liou, Li-C. Wang, K.-T. Cheng, J. Dworak, M.R. Mercer, R. Kapur, and T. W. Williams, “Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes,” Proc. of Design Automation Conference, 2002, pp. 371-374.

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在后羿平台上以進階交流掃描為基礎的延遲測試與特徵描述

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