具混和式切換及背景誤差校正之12位元連續漸進式類比數位轉換器

12-bit SAR ADC with Mixed Switching and Background Offset Calibration

謝易成(Yi-Cheng Hsieh)

指導教授 ： 洪崇智

國立交通大學/電機學院/電機工程系所/碩士(2017年)

摘要

本論文為連續漸進暫存器(SAR)類比數位轉換器(ADC)由台灣積體電路製造股份有限公司1P6M0.18um互補式金氧半製程來實現，並具有混和開關切換和校正比較器輸入偏移電壓的機制。在這裡運用了混和開關切換─結合融合式電容切換與單調式切換來節省功率消耗。除此之外，此次設計也運用了電容充放電的電荷泵之類比校正方式以及調整電容負載之數位校正方式來達到較低的偏移電壓。
利用電荷泵校正機制之10百萬赫茲連續漸進式類比數位轉換器在模擬情況為1.8V電壓源且輸入頻率為1.975百萬赫茲時，模擬結果可達66.73dB的訊號雜訊失真比與10.79
bits的有效位元數，整體功率消耗為736.23μW並且FOM為41.58fJ/conversion-step。利用可調整式電容校正機制之50千赫茲連續漸進式類比數位轉換器在模擬情況為1.8V電壓源且輸入頻率為9.876千赫茲時，模擬結果可達72.56dB的訊號雜訊失真比與11.76bits的有效位元數，整體功率消耗為18.31μW並且FOM為105.59fJ/conversion-step。
利用電荷泵校正機制之10百萬赫茲連續漸進式類比數位轉換器在1.8V電壓源和1百萬赫茲的操作頻率下，當輸入頻率為12.3444千赫茲時，量測結果為39.50dB的訊號雜訊失真比及6.27bit的有效位元數，總功率消耗為186.3762µW。

關鍵字

連續漸進式比較器 ； 校正

並列摘要

This thesis presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with mixed switching and offset calibration in TSMC 0.18-µm process. To reduce the switching energy and save the total capacitance, a mixed switching procedure is applied. The mixed switching procedure combines the merged capacitor switching with monotonic switching. Beside, two dynamic comparators with charge pump and adaptive capacitor calibration to achieve lower offset are used.
For the SAR ADC with charge pump at 1.8V supply voltage and 10MHz sampling rate, simulation results achieve 66.73dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 10.79 effective number of bits (ENOB) at 1.975MHz input frequency. Its power consumption is 736.23µW and figure-of-merit (FOM) is 41.58 fJ/conversion-step. For the SAR ADC with adaptive capacitor at 1.8V supply voltage and 50KHz sampling rate, simulation results achieve 72.56dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 11.76 effective number of bits (ENOB) at 9.876KHz input frequency. Its power consumption is 18.31µW and figure-of-merit (FOM) is 105.59 fJ/conversion-step.
For the SAR ADC with charge pump at 1.8V supply voltage and 1MHz sampling rate, measurement results achieve 39.50dB signal-to-noise-and-distortion-ratios (SNDR) which lead to 6.27 effective number of bits (ENOB) at 12.3444KHz input frequency. Its power consumption is 186.3762µW.

並列關鍵字

SAR ADC ； Calibration

參考文獻

[1] Y. Zhou, B. Xu, Y. Chiu, "A 12 bit 160 MS/s two-step SAR ADC with background bit-weight calibration using a time-domain proximity detector", IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 920-931, Apr. 2015.

[2] C. Wu and J. Yuan, "A 7 Bit 800MSs SAR ADC with Background Offset Calibration," in Circuits and Systems (ISCAS), 2016 IEEE International Symposium on, pp. 1038-1041, Aug. 2016.

[3] H. Huang et al., "A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS with Passive Residue Transfer", IEEE ASSCC Dig. Tech. Papers, pp. 289-292, Nov. 2015.

[4] L. Yu, K. Doris, H. Hegt, and A. H. M. van Roermund, "An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 906-914, 2012.

[5] N. Verma and A. P. Chandrakasan, "An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes," Solid-State Circuits, IEEE Journal of, vol. 42, pp. 1196-1205, 2007.