記憶體陣列測試與診斷之效率提升

Improving Testing and Diagnosis Efficiency of Regular Memory Arrays

吳宗祐(Tsung-Yu Wu)

指導教授 ： 吳誠文

國立清華大學/電機資訊學院/電機工程學系/碩士(2009年)

https://doi.org/10.6843/NTHU.2009.00728

摘要

內嵌式記憶體已經很廣泛的被運用在 SOC 上，而隨著多核心晶片的發展，在晶片中的記憶體核的個數也快速的上升。因為記憶體細胞擁有高密度與容量，發生錯誤的機率相對的也較高，因此，記憶體的測試、診斷與修復顯得更加重要，關係到整顆晶片的良率。記憶體測試的方式已經有許多討論，BIST (內嵌自我測試) 電路是一個常用的方法，BIST 提供可存取性、可延展性、可程式的能力以及低面積負擔。傳統的 BIST 所測試的記憶體核個數較少，對於由記憶體核所組成的記憶體核陣列的測試卻仍有改進之處：傳統的 BIST 在測試多顆記憶體核時，診斷錯誤的過程會花費很長的診斷時間，因為這個流程是循序的而非平行的。
　　BRAINS 是一個自動產生BIST 的產生器。BRAINS 提供平行測試、硬體共享、全速測試、診斷、分組與測試規畫等功能。這篇論文根據 BRAINS改良為 BRAINS_A (BRAINS for Regular Memory Arrays)。BRAINS_A將原本在測試模式中的平行測試觀念運用在診斷模式中，使得診斷可以平行執行，大幅降低測試時間。在診斷的過程中，BRAINS_A 會搜尋錯誤的記憶體，僅針對錯誤記憶體診斷。BRAINS_A 也提供了提前終止的機制，可以在偵測到錯誤的時候就停止測試。在進行診斷的過程中，BRAINS_A 提供了資料壓縮 (Compression) 的功能，當很多錯誤細胞同時發生的時候，會有較好的壓縮率。在測試32顆記憶體陣列的實驗結果顯示，BRAINS_A 相較於 BRAINS，在測試時間上減少了 6 到 23 倍，而面積只增加了 10% 到 17%。

關鍵字

記憶體陣列 ； 記憶體測試 ； 記憶體診斷

並列摘要

Embedded memory cores are widely used in the SOC, and the area percentage of embedded memory cores in the SOC is growing rapidly. Since the high density and capacity of embedded memory cells, the probability of faulty bits is high and the chip yield will be affected. Therefore, embedded memory testing, diagnosis and repair are required to improve the testability, yield and reliability. Built-in Self-Test is one of the most used design-for-test (DFT)
circuit to test embedded memory. It provides accessibility,
scalability, programmability, low area overhead and flexibility. The conventional BIST is attached to each memory core or shared by several cores; however, for the regular memory array with large core number, the conventional BIST methods become inefficient in terms of
test time and area overhead.

BRAINS is a BIST generator to generate the BIST design. It features parallel testing, hardware sharing, at-speed testing, diagnosis support and grouping/scheduling. However, in testing the multi-core array, the testing and diagnosis flow is not efficient that the total test time is directly proportional to the memory cores. In this work, we propose a BIST generator BRAINS\_A which is based on
the BRAINS design that can generate BIST circuit to test the memory array efficiently. BRAINS\_A supports early stop in the test mode and automatic parallel diagnosis with data compression in the diagnosis mode. With these modified functions, the testing and diagnosis flow becomes simple and the overall test time can be reduced by 6 to 23 times with area overhead increased from 10\% to 17\% in the experiment of a 32-core memory array.

並列關鍵字

Memory Array ； Memory Testing ； Memory Diagnosis

參考文獻

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