MOHOS結構之電容與電晶體在記憶體上的應用與電性分析

Electrical Characterization of Metal-Oxide-High-k dielectric-Oxide-Semiconductor(MOHOS) Capacitors and Transistors for Memory Applications

徐信豪(Hsin-Hao Hsu)

指導教授 ： 李雅明

國立清華大學/電機資訊學院/電子工程研究所/碩士(2006年)

https://doi.org/10.6843/NTHU.2006.00213

摘要

我們已經研究金屬-氧化物-高介電係數介電層-氧化物-矽結構(MOHOS-type flash memory) 並使用HfO2 和Dy2O3 作為高介電係數介電層結構的電容器和電晶體。並對元件作基本的電性量測與可靠度分析；首先藉由不同的儲存層材料的差異，探討其對MOHOS元件電特性的影響；再來探討不同RTA溫度對儲存層特性的影響。
由MOHOS電容結構的量測結果，在J-V curve的測量上，使用HfO2當作電荷儲存層的樣品在10V的外加電壓下RTA 600℃時有最小的漏電流密度大小為10-6 A/cm2；而使用Dy2O3當作電荷儲存層的樣品在10V的外加電壓下RTA 400℃有最小的漏電流大小密度為10-8 A/cm2。
由MOHOS電晶體結構的結果，在基本電性上的表現，如：ID-VD，ID-VG及C-V等，皆證明電晶體能夠正常的操作，使用Dy2O3材料當作電荷儲存層的樣品，在基本電晶體電性方面其次臨界斜率為St=104.2 mV/dec、遷移率為276 cm2/V-sec，在記憶體特性方面其寫入速度為+12V經過10 ms能夠有1.1V的Vth差、I-V memory window大小為1.85V、retention time為2x108秒(6年)。

關鍵字

MOHOS ； 非揮發性記憶體

並列摘要

Abstract

Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal–oxide–high-k dielectric–oxide–silicon (MOHOS) capacitors and transistors are fabricated using HfO2 and Dy2O3 high-k dielectrics as the charge storage layer. The Al/SiO2/Dy2O3/SiO2/Si capacitors have a C-V memory window of 1.88V. The leakage current density of the Al/SiO2/Dy2O3/SiO2/Si capacitor is 10-8A/cm2 at 10V. The leakage current density of the Al/SiO2/HfO2/SiO2/Si capacitor is 10-6/cm2 at 10V. The leakage current density of the Al/SiO2/Dy2O3/SiO2/Si capacitor is lower than that of Al/SiO2/HfO2/SiO2/Si capacitor at the same bias voltage.
The programming speed of Al/SiO2/Dy2O3/SiO2/Si transistor is characterized by a Vth shift of 1.1V with a programming stress pulse voltage of 12V for 10 ms. After a +12V, 0.1 s program pulse and a -12V, 0.5 s erase pulse, the Al/SiO2/Dy2O3/SiO2/Si transistors can keep a ΔVth window of 0.5V for 2x108 seconds. The corresponding numbers for Al/SiO2/HfO2/SiO2/Si transistors are 100 ms and 2x104 seconds. The better performance of the Al/SiO2/Dy2O3/SiO2/Si transistors is attributed to the larger conduction band offset at the Dy2O3/SiO2 interface (2.3eV) versus 1.6eV at the HfO2/SiO2 interface.

參考文獻

[1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” IEEE Trans. Electron Devices, vol. 14, no. 9, pp.629-629, 1967.

[2] D. Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable MOS-ROM,” IEEE ISSCC Dig. Tech. Papers, pp. 80-81, 1971.

[3] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connell, and R.E. Oleksiak, “The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,” IEDM Tech. Dig., 1967.

[4] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, T. Wang, S. Pan, C. Y. Lu, and S.H. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell,” IEDM Tech. Dig., pp. 32.6.1 -32.6.4., 2001.

[5] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakaca, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-K charge trapping layer,” IEEE Symp. VLSI Technology Digest of Technical, pp. 24-28, 2003.