負電容場效電晶體與鐵電電晶體於邏輯及記憶體應用之元件模型與探討

Modeling and Investigation of Negative Capacitance FETs and Ferroelectric FETs for Logic and Memory Applications

尤韋翔(Wei-Xiang You)

指導教授 ： 蘇彬

國立交通大學/電機學院/電子工程系所/博士(2019年)

摘要

本論文針對新興的負電容場效電晶體(negative-capacitance FET)及鐵電電晶體(ferroelectric FET)應用於未來低功耗邏輯及嵌入式記憶體應用提供完整的評估與分析。在此論文中，我們各別對於鐵電閘控電晶體(ferroelectric-gated transistor)用於開關及記憶體之面相，考慮了元件-電路間相互影響(interaction)和共同最佳化(co-optimization)以呈現鐵電閘控電晶體在元件/電路層面的潛力及隱憂。
著眼於邏輯應用，如何透過元件設計使負電容場效電晶體達到較大電壓操作範圍未遲滯的陡峭開關是一相當關鍵之課題。藉由一可微縮且經良好驗證之模型，在考慮深埋氧化層(buried oxide)厚度及背閘極偏壓效應(back-gate biasing effect)下，我們建構了以二維過渡金屬硫屬化合物為通道之金屬-鐵電-金屬-絕緣體-半導體結構負電容場效電晶體之元件設計空間。我們的結果指出，藉由採用薄的深埋氧化層及施加適當大小的反向背閘極偏壓效應可擴張元件之設計空間並達到最佳化設計，但特別對於採用薄深埋氧化層的二維負電容場效電晶體而言，因負電容作用造成的特殊基板偏壓效應也需要進行考慮。
藉由一理論推導之通用模型，我們也檢視了技術上較易實現之金屬-鐵電-絕緣體-半導體閘極層(gate stack)二維負電容場效電晶體在絕緣層上覆矽(SOI)和雙閘極(DG)結構間負電容效應之本質差異。此外，為了達到最佳化設計，深埋氧化層厚度對絕緣層上覆矽結構二維負電容場效電晶體之負電容效應之影響亦有所著墨。我們的研究指出，不同於對稱的雙閘極結構，絕緣層上覆矽結構中，獨立背閘極的存在會產生一映襯於背閘極具電壓相關性的內在電荷(internal charge)並使負電容效應可在次臨界區域下作用。雖然透過薄化深埋氧化層可改善絕緣層上覆矽結構負電容場效電晶體之次臨界斜率，但過薄的深埋氧化層厚度會產生一具強烈電壓相關性的鐵電電容惡化元件之平均次臨界斜率。
隨著閘極長度的微縮，藉由數值模擬結合考慮了汲極耦合效應之解析次臨界模型，我們系統性的探討了金屬-鐵電-金屬-絕緣體-半導體結構二維負電容場效電晶體之短通道效應。而通過高介電夾層的邊際電場(fringe field)對短通道二維負電容場效電晶體次臨界特性之影響亦有所著墨。我們的結果顯示，由於汲極耦合對負電容效應之影響，二維負電容場效電晶體展現了獨特的短通道行為。此外，雖然高介電夾層的使用可以進一步改善短通道二維負電容場效電晶體之次臨界特性，但過大的高介電常數會造成非線性的次臨界電流-電壓特性並嚴重惡化二維負電容場效電晶體的平均次臨界斜率(subthreshold swing)。
除了金屬-鐵電-金屬-絕緣體-半導體結構負電容場效電晶體外，我們也探討了金屬-鐵電-絕緣體-半導體負電容鰭式場效電晶體之短通道效應及靜電完整性(electrostatic in-tegrity)並與鰭式場效電晶體相比較。藉由一經良好驗證之解析次臨界模型，我們檢視了等電位能量圖跟剖面電位能量隨閘極及汲極電壓的變化並發現，與鰭式場效電晶體相比，負電容鰭式場效電晶體天生具有較好的靜電完整性。此外，適當的側壁空間層(spacer)設計可進一步增強負電容鰭式場效電晶體之負電容效應及靜電完整性並可作為一延續鰭式場效電晶體微縮之方式。
為了能夠評估金屬-鐵電-絕緣體-半導體負電容鰭式場效電晶體所組成電路之效能，我們發展了一以表面電位為基礎且與BSIM-CMG相容之短通道金屬-鐵電-絕緣體-半導體負電容鰭式場效電晶體電路簡化模型。金屬-鐵電-絕緣體-半導體負電容場效電晶體特有的局部電荷分布效應可在不須進行局部電荷加成下自然地融入在電壓-電流模型中。藉由我們的模型，我們首次透徹地評估及分析了採用十四奈米極低功耗負電容鰭式場效電晶體之超大型積體電路次系統級邏輯電路。根據我們探索的三變數(待機功耗/開關能量/延遲)等位圖，我們發現在一給定的待機功耗及延遲下，相較於鰭式場效電晶體，採用負電容鰭式場效電晶體之高速加法器其開關能量消耗可以減少約六十個百分比。我們也指出了，除了陡峭的次臨界斜率和導通電流(ION)，負電容鰭式場效電晶體獨特的反向臨界電壓隨汲極電壓相依性(意即:負的汲極誘導能障降低(DIBL))不僅是可接受的，亦有利於靜態(static)及傳導電晶體(pass-transistor)邏輯電路之效能，特別是在低操作電壓下的傳導電晶體邏輯電路。
為了使靜態隨機存取記憶體(SRAM)在較低的操作電壓下可牢靠的作用同時只佔據較小的面積，我們提出了一利用負電容鰭式場效電晶體反相器所形成的獨特遲滯電壓轉換特性發展出混和式抗讀寫干擾之四顆電晶體靜態隨機存取記憶體。此四顆電晶體靜態隨機存取記憶體的功能性已由積體電路通用模擬程式(SPICE)電路模擬進行分析與實現。由於其本質上具有優異之抗讀寫干擾能力，因此我們也展現了在四顆電晶體靜態隨機存取記憶體內執行記憶體內運算(in-memory computation)之可靠性。除了混和式四顆電晶體靜態隨機存取記憶體外，我們也提出了採用了鰭式場效電晶體及遲滯負電容鰭式場效電晶體之混和式八顆電晶體非揮發性靜態隨機存取記憶體(nvSRAM)。此八顆電晶體非揮發性靜態隨機存取記憶體之建構是藉由增加兩顆遲滯負電容鰭式場效電晶體於傳統六顆電晶體靜態隨機存取記憶體中用於連接儲存點及傳導電晶體。根據這樣的架構，八顆電晶體非揮發性靜態隨機存取記憶體可在與傳統六顆電晶體靜態隨機存取記憶體有著相匹敵的效能及能量消耗下實現其非揮發特性。
著眼於嵌入式非揮發性記憶體應用，此章節以靜態Preisach模型探討了以金屬-鐵電-金屬-絕緣體-金屬及二維通道場效電晶體為結構之鐵電非揮發性記憶體之去極化電場(depolarization field)(記憶體資訊保存(retention)之一關鍵指標)及記憶窗(memory window)特性。我們也探討了閘極長度微縮對具有不同側壁空間層設計之二維鐵電電晶體記憶窗之影響。我們的研究指出，當鐵電層操作在小遲滯圈(minor loop)中，具強烈等效氧化層厚度相依性之極化電荷會導致去極化電場隨等效氧化層變薄而增大。因此當給定一記憶窗大小，較厚的等效氧化層設計有利於降低去極化電場。此外，我們也指出，二維鐵電電晶體可藉由側壁空間層之設計使強反轉(strong inversion)及累積(accumulation)區域下的內在電荷提高並進一步極化鐵電層，因此記憶窗可隨著閘極長度的縮短而大幅增加。我們的研究提供了鐵電電晶體用於非揮發性記憶體之設計藍圖。

關鍵字

負電容場效電晶體 ； 鐵電電晶體 ； 二維過渡金屬硫屬化合物 ； 鰭式場效電晶體 ； 邏輯電路 ； 非揮發性記憶體 ； 靜態隨機存取記憶體 ； 記憶體內運算 ； 去極化電場 ； 記憶窗

並列摘要

This dissertation provides an extensive assessment of emerging negative-capacitance FETs (NCFETs) and ferroelectric FETs (FeFETs) for future low-power logic and embedded memory applications. Device-circuit interaction and co-optimizations for the ferroelec-tric-gated transistor used as a switch or a memory are considered, respectively, to demonstrate the potential and concerns of the ferroelectric-gated transistors from the device/circuit perspective. Through our analysis, the in-depth understanding of the advantages, constraints, trade-off and merits of the ferroelectric-gated transistors for logic/memory applications is provided.
How to achieve a wide voltage range steep slope without the hysteresis through the de-vice design is a critical topic for NCFETs targeting at logic applications. With the aid of a verified scalable model, the device-design space for the met-al-ferroelectric-metal-insulator-semiconductor (MFMIS) type NCFET with a 2D transition metal dichalcogenide (TMD) channel (2D-NCFET) has been explored considering the impact of buried oxide thickness (BOX) and back-gate biasing effect. Our results indicate that, a thin BOX and an adequate reverse back-gate bias can be applied to maximize the design space and achieve the optimum design while the distinctive body effect due to the action of negative capacitance (NC) should also be considered especially for 2D-NCFET with thin BOX.
Using a theoretically derived general model, the intrinsic difference in NC effects be-tween silicon-on-insulator (SOI) and double-gate (DG) structures has also been investigated with a technologically more viable metal-ferroelectric-insulator-semiconductor (MFIS) type gate stack 2D-NCFET. Besides, to achieve an optimal design, the impact of BOX thickness on the NC effect of SOI 2D-NCFETs is addressed. Our study reveals that, different from the symmetric DG structure, the existence of an independent back-gate in the SOI structure re-sults in a bias-dependent internal charge mirrored from the back-gate, thus enabling the NC-effect below threshold. Although the SS of the SOI structure NCFET can be improved by thinning BOX, an excessive thinning of BOX may result in a strong-bias dependent ferroelectric capacitance which degrades the average SS.
With the scaling of gate length (Lg), the short-channel effects (SCEs) in MFMIS-type 2D-NCFET have been systematically investigated through numerical simulations corroborated by an analytical subthreshold model that physically considers the impact of drain coupling. The impact of fringe field through the high-k interlayer dielectric on the subthreshold characteristics of the short-channel 2D-NCFET has also been addressed. Our study reveals that, due to the impact of drain coupling on the NC effect, the 2D-NCFET exhibits distinct short-channel behaviors. Additionally, the utilization of high-k interlayer can further improve the subthreshold characteristics of the short-channel 2D-NCFET, while an excessively large interlayer dielectric constant may significantly degrade the average SS due to the existence of nonlinear subthreshold I-V.
In addition to the MFMIS-type NCFET, the investigation of SCEs and electrostatic in-tegrity (EI) in MFIS-type NC-FinFET have also been conducted and compared with the FinFET counterparts. With the aid of a well-verified analytical subthreshold model, our study shows that the NC-FinFET inherently possesses a superior electrostatic integrity than the baseline FinFET by examining the equi-potential-energy contour maps and the changes of potential energy profiles with various gate and drain biases. In addition, an adequate spacer design can be utilized to further enhance the NC effect and the EI for NC-FinFETs and serves as a way to extend the FinFET scaling.
For the purpose of evaluating the performance of circuits using MFIS-type NC-FinFETs, we have developed a surface-potential-based short-channel MFIS-type NC-FinFET compact model compatible with BSIM-CMG. The local charge distributed effect is naturally included in the drain current model without the need of local charge summation. Using our model, the performance of VLSI subsystem-level logic circuits employing 14nm ULP NC-FinFETs are comprehensively evaluated and analyzed for the first time. Based on our explored three-variable standby-power/switching-energy/delay contour plots, the switching-energy of the high-speed adders with NC-FinFETs can be reduced by ~60% compared with the FinFET counterpart for a given standby-power and delay. It has also been indicated that, in addition to the steep slope and ION, the unique inverse Vds-dependency of VT characteristic (i.e., the negative DIBL) of NC-FinFETs is not only acceptable but beneficial to the performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL style at low supply voltage.
To achieve a robust functionality of the SRAM operating at a lower supply voltage with a small area overhead, we have proposed a disturb-resistant hybrid 4T SRAM cell enabled by a hysteretic VTC of the NC-FinFET inverter. The functionality of the 4T SRAM has been demonstrated by SPICE simulation. Due to its inherent disturb-resistant characteristic, the robustness of performing the in-memory computation with 4T SRAM cells has been demon-strated. In addition to the hybrid 4T SRAM cell, we have also proposed a hybrid 8T nonvola-tile SRAM (nvSRAM) cell employing FinFETs and hysteretic NC-FinFETs. The proposed 8T nvSRAM cell is built with two hysteretic NC-FinFETs connecting the storage nodes and the access pass transistors in the conventional 6T SRAM. Based on this architecture, the nonvolatility of the 8T nvSRAM can be achieved with the comparable performance and en-ergy consumption of the conventional 6T SRAM.
To target at embedded nonvolatile memory (NVM) applications, we investigate the de-polarization field Edep (i.e., a critical index for the memory retention) and memory window (MW) of the ferroelectric NVM with MFMIM and 2D-channel FET structures within the static Preisach modeling framework. The impacts of Lg scaling on the MW of 2D-FeFETs with various spacer materials are also investigated. Our study indicates that, for the ferroelectric operating within the minor loops, the strong equivalent oxide thickness (EOT) dependence of polarization results in the increase in Edep with decreasing EOT, so thicker EOT is favorable to achieve a lower Edep for a targeted MW. Additionally, we have also pointed out that, with the spacer design, the MW of the 2D-FeFET can be significantly improved with decreasing Lg due to the enhanced internal gate charge at strong inversion and accumulation to polarize the ferroelectric. Our study may provide insights for NVM design using FeFETs.

並列關鍵字

Negative-Capacitance FET ； Ferroelectric FET ； 2D Transition-Metal-Dichalcogenide ； FinFET ； Logic Circuits ； Nonvolatile Memory ； SRAM ； In-Memory Computation ； Depolarization Field ； Memory Window

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