完全邏輯製程相容之單接觸點電阻式記憶體及其垂直雙極性驅動電晶體之研究

快閃記憶體是唯一量產的非揮發性半導體儲存技術，且在現今的高科技電子產品市場中，佔有主宰的地位。但是快閃記憶體隨著製程的微縮，將面臨到許多挑戰，諸如氧化層漏電、軟性崩潰以及密度極限等。因此開發新型的非揮發性記憶體，追求更佳的儲存密度、微縮特性和更快的存取速度有其必要性。電阻式記憶體是近年來許多記憶體相關研究的焦點，由於它的非揮發性、耐用度佳且容易微縮等優勢，使它成為未來能取代快閃記憶體的候選人之一，其簡單的架構和小尺寸也能應用在發展模擬大腦運作的仿神經電路。本論文提出一種能由一個接觸點來定義單元面積的電阻式記憶體架構，命名為單接觸點電阻式記憶體(1C-RRAM)，以接觸點電阻性薄膜做為電阻轉換元件，埋藏在接觸點下方的新型垂直雙極性電晶體用來選取及驅動，此結構能使單元面積微縮到極小的尺寸。本研究將討論1C-RRAM的架構及製造過程，它已經在65奈米CMOS邏輯製程中製造出來，無需增加額外光罩，也就是說此1BJT+1R的垂直式電阻式記憶體結構可完全相容於邏輯製程。除此之外，我們也將討論記憶體陣列的佈局方式，以及在不同製程技術下的垂直雙極性電晶體特性，最後以實際量測驗證1C-RRAM的可行性，在此期許1C-RRAM能夠為未來的高密度內嵌式非揮發性記憶體應用帶來解決之道。

關鍵字

記憶體

並列摘要

Flash memory is the only non-volatile semiconductor storage technology for mass production, and dominates the market of high-technology electronic products nowadays. However, flash memory suffers from many of challenges with scaling down, such as gate oxide leakage, soft breakdown, density limit, etc. For this reason, it is necessary to develop a new NVM, in order to pursue higher density, scalability and faster access speed. Resistive Random Access Memory has become the focus of many memory studies in recent years, it's a candidate as the next-generation NVM for the future, as a result of its strong advantages in scalability, non-volatility, endurance. Its simplicity as well as small size push RRAM device into the development of neuromorphic circuits, which simulates the functions and operations a brain. In this thesis, we propose a RRAM cell defined by a single contact area which named Single Contact RRAM (1C-RRAM). Utilizing contact resistive film as resistive switching element, driving and selecting by a novel vertical bipolar transistor underneath, hence 1C-RRAM can be further scaled to a small cell. In this study, we discuss the fabrication and architecture of 1C-RRAM, fabricated by 65nm CMOS logic process without any extra mask. In other words, this 1BJT+1R structure is fully CMOS-compatible. In addition, we investigate the layout of cell arrays and BJT characteristics in different technology; finally, 1C-RRAM has been successfully demonstrated by measurement result. We believe that 1C-RRAM is a very promising solution for future high density and embedded NVM applications.

並列關鍵字

CMOS ； BJT ； RRAM

參考文獻

[1] Yuan Heng Tseng et al, “High density and ultra small cell size of Contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits”, in IEDM Tech. Dig., 2009, pp109-112.

[2] Yuan Heng Tseng et al, “A New High-Density and Ultra small-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits”, in IEEE Trans. Electron Devices, vol. 58, no. 1, p. 53-58, Jan. 2011.

[3] Ching-Hua Wang et al, “Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process”, in IEDM, pp. 29.6.1-29.6.4, 2010

[4] Ching-Hua Wang et al, “Three-Dimensional 4F2 ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process” , in IEEE Trans. Electron Devices, vol. 58, no. 8, p. 53-58, Aug. 2011.

[5] Baek, I.G. et al, “Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses”, in IEDM Tech. Dig., 2004

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完全邏輯製程相容之單接觸點電阻式記憶體及其垂直雙極性驅動電晶體之研究

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