平面式獨立雙閘極多晶矽SONOS記憶體元件以及非對稱式蕭特基能障薄膜電晶體之製作與特性分析

本篇論文探討平面式獨立雙閘極(planar independent double-gated)多晶矽SONOS記憶體元件的特性。平面式獨立雙閘極多晶矽SONOS記憶體元件具有兩個可獨立操控的閘極，所以有兩種讀取的操作模式。本論文中所製造的元件其閘極介電層分別為二氧化矽及二氧化矽-氮化矽-二氧化矽堆疊層兩種。分析兩種不同讀取模式對感測窗口大小(memory window)特性的影響，發現當選用二氧化矽-氮化矽-二氧化矽堆疊層為閘極介電層之閘極當驅動閘極(driving gate)時，SONOS記憶體元件具有比較大的感測窗口，而且窗口大小與施加於控制閘極(control gate)的偏壓無關。根據這些分析，我們可以將此元件應用在創新的SONOS NAND 串列中，其主要優點為低的熱預算(thermal budget)、低的讀取干擾(read disturb)、以及簡易的製程步驟。對於未來高密度的三維堆疊非揮發性記憶體技術來說，此元件的應用相當具有可行性。此外，在本論文中利用了低成本的雙重微影成像技術成功地製作出非對稱式蕭特基能位障(Schottky-barrier)薄膜電晶體。非對稱式蕭特基能位障薄膜電晶體是以矽化鉑(PtSi)接面作為元件的源極，而氟化硼離子摻雜區則是作為元件的汲極。如此一來可以有效的降低漏電流使元件顯示出單極(unipolar)的傳輸特性。除此之外，我們研究也發現，當閘極驅動電壓(gate overdrive)夠大且使用的閘極介電材質為氮化矽-二氧化矽堆疊層時，元件的輸出特性會展現負電阻現象，歸因於源極端熱電洞注入的機制。在文獻上已有蕭特基元件熱電子注入的報導，熱電洞注入則是首次揭露的發現。

關鍵字

蕭特基能障；獨立雙閘極；矽化鉑；多晶矽

並列摘要

In this thesis, we study the characteristics of planar independent double-gated (IDG) polycrystalline silicon (poly-Si) silicon–oxide–nitride–oxide–silicon (SONOS) devices. Two different operation modes can be adopted in the planar IDG poly-Si SONOS devices having two independent gates. The fabricated devices in this thesis employ oxide and oxide-nitride-oxide (ONO) stack as dielectrics for the two independent gates, respectively. We analyze the size of memory window under different operation modes. Our theoretical analysis and experimental data indicate that the operation mode with the ONO gate serving as the driving gate and the oxide gate as the control gate can obtain a larger memory window. Besides, the memory window of this operation mode is independent of the bias applied to the control gate. Based on these features, the applications of innovative SONOS NAND string with IDG configuration are developed. The favorable merits are low thermal budget, low read disturb and simple fabrication. This device has potential to be applied to the future high-density 3-D non-volatile memory technology. Next, asymmetric Schottky barrier (ASSB) thin film transistors (TFTs) are successfully fabricated by a low-cost double patterning technique in this thesis. The ASSB-TFT devices feature a PtSi Schottky junction at the source-side and a BF2+-doped drain. This structure can significantly lower off-state leakage current and exhibit unipolar behavior. We also investigate the source-side hot hole injection mechanism triggered by the sharp energy band bending. The negative-differential conductance (NDC) behavior due to dynamic hole trapping is observed when an nitride/oxide stack is used as the gate dielectric. This is attributed to the fact that hot holes generated at the source-side could surmount the barrier (height ~2eV) at the nitride/channel interface and get trapped in the dielectric. It is worth mentioning that the NDC behavior is absent when oxide, which has a higher barrier height of 4.7eV for holes, is used as the gate dielectric. To the best of our knowledge, this is the first report on the observation of dynamic hole trapping in SB devices.

並列關鍵字

Schottky barrier ； Independent Double-Gated ； PtSi ； poly-Si

參考文獻

[1] Y. Nishi, “Insulated gate field effect transistor and its manufacturing method,” Patent 587 527, 1970.

[2] M. P. Lepselter and S. M. Sze, “SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain,” Proc. IEEE, vol. 56, no. 8, pp. 1400–1402, Aug. 1968.

[3] W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, “Analysis of short channel Schottky source/drain metal-oxide-semiconductor field-effect transistor on SOI substrate and demonstration of sub-50 nm n-type device with metal gate,” Jpn. J. Appl. Phys., vol. 38, pp. 6226–6231, 1999.

[4] C. K. Huang, W. E. Zhang, and C. H. Yang, “Two-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nm,” IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 842–848, Apr. 1998.

[5] M. Sugino, L.A. Akers, and M.E. Rebeschini, “CMOS latch-up elimination using Schottky barrier PMOS,” IEDM Tech. Dig., vol. 28, pp. 462–465, 1982.

國際替代計量

平面式獨立雙閘極多晶矽SONOS記憶體元件以及非對稱式蕭特基能障薄膜電晶體之製作與特性分析

全文下載

主題瀏覽