本篇論文結合多晶矽及全包覆式的結構製造出側壁鑲嵌全包覆式多晶矽奈米線SONOS記憶體,不必使用先進的黃光技術就能製造出奈米尺度的元件,我們除了使用傳統的固相結晶法(Solid phase crystallization)來結晶多晶矽通道(Poly-Si channel),還加入快速退火(Rapid thermal annealing)製程來提升結晶性並改善元件的傳輸特性。此外,我們更針對不同結晶性的SONOS記憶體採用不同寫入/抹除(Programming/Erasing)操作機制像是通道熱電子注入(Channel hot electron injection)、場穿隧注入(Fowler-Nordheim tunneling)、能帶間穿隧誘發熱電子注入(Band to band tunneling induced hot electron injection)所表現的寫入/抹除速度(Programming/Erasing speed)特性來深入討論,我們發現不同的操作機制對於結晶性有不同的敏感程度,通道熱電子注的操作機制相較於場穿隧注入的操作機制對結晶性更加敏感;能帶間穿隧誘發熱電子注入的操作機制中,在能帶間穿隧誘發熱電子注入操作機制中,水平電場相較於垂直電場對於結晶性更加敏感。SONOS記憶體的可靠性議題像是保存(Retention)特性、耐久(Endurance)特性也一同被討論,而整體元件的操作偏壓都小於10伏特,對於低功耗的應用非常有前景。
In this thesis, we combine poly-Si and GAA structure to fabricate sidewall damascene GAA poly-Si nanowire SONOS memory. This process didn’t involve advanced lithography and still fabricated nanoscale transistor. Besides we employed the method of solid phase crystallization (SPC) to crystallize poly-Si channel, rapid thermal annealing process was applied to advance the crystallinity and improve the transfer characteristics. Furthermore, we focused on crystallinity effect on various programming/erasing operation mechanisms such as channel hot electron injection (CHE), Fowler-Nordheim tunneling (FN), band to band tunneling induced hot electron injection (BBHE) whose programming/erasing speed characteristics to make an in-depth discussion. We found various operation mechanisms have different sensitivity to crystallinity. CHE programming mechanism is more sensitive to crystallinity than FN operation mechanism, and lateral electric field is more sensitive to crystallinity than vertical electric field under BBHE mechanism. The reliability issues such as retention characteristics and endurance characteristics were also discussed. All of operation voltage was sub-10 V which means it is highly promising to low power application.