通道截面形狀對多晶矽奈米線非揮發性記憶體元件操作特性影響之研究

在本篇論文中，我們利用本實驗室最近發展出的多晶矽奈米線製程來製作SONOS元件。此製程無須使用先進且昂貴的設備，其製作流程簡單且極富彈性。藉由修改幾個關鍵的製程步驟，我們製作了兩種不同截面形狀(三角形和矩形)但尺寸接近的奈米線元件，並且去分析與比較兩者之間的特性。結果顯示，三角形奈米線元件呈現出較好的次臨界擺幅(subthreshold swing)，且在一開始操作下具有比較快的寫入和抹除速度，但隨著操作時間拉長會逐漸趨於飽和，矩形奈米線的臨界電壓飄移則會逐漸地超過三角形奈米線。在可靠度方面，在經歷忍耐度(endurance)測試後，在尖角處會有大量的介面缺陷產生，使得次臨界擺幅及臨界電壓均會上升。而在電荷保持(retention)方面，由於在尖角處會有較大的電場產生，被捕捉住的電子容易於此處產生漏電的現象，因此在經過電荷儲存測試下，三角形奈米線的記憶窗(memory window)縮減速度比矩形奈米線快。此外，我們採用氧化鋁為阻擋氧化層以及二氧化鉿為電荷捕捉層，製作與分析TAHOS奈米線記憶體元件。然而實驗的結果卻發現沒有令人滿意的記憶體特性。大部份儲存在二氧化鉿的電子會在過薄氧化鋁中遷移並漏出至控制閘，導致特性的劣化。

關鍵字

奈米線電晶體；環繞全閘極；電荷儲存能力；忍耐度

並列摘要

In this thesis, we have employed simple and flexible methods that were recently developed by our group to fabricate NW devices. By modifying some major steps of fabrication procedure, GAA NW SONOS devices with two different shapes but comparable feature size of NW cross-section were fabricated and characterized. Compared with rectangular-shaped NW (R-NW) devices, triangular-shaped NW (T-NW) devices possess superior SS. However, even though T-NW devices have higher P/E speed in the early stage of P/E operation, the Vth shift of R-NW devices overtakes gradually as P/E proceeds. For endurance test, the SS becomes worse with increasing cycles for both devices due to the corner effect. For retention test, the memory window for T-NW devices degrades faster than that for R-NW devices,indicating that the trapped electrons tend to leak out more easily at the sharper corners. We have also fabricated GAA NW TAHOS devices with the adoption of high-κ materials. However, the fabricated TAHOS devices exhibit poor memory characteristics according to the experimental results. Most of the stored electrons would migrate inside the thin Al2O3 and eventually leak out to the control gate. Therefore, the process conditions need to be refined in future device fabrications.

並列關鍵字

nanowire FET ； gate-all-around ； retention ； endurance ； SONOS ； TAHOS

參考文獻

Chapter 1

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[1.5] J. P. Colinge, M. H. Gao, A. R. Rodriguez, H. Maes, and C. Claeys, "Silicon-on-insulator gate-all-around device," IEDM Tech. Dig., pp.595-598, 1990.

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[1.7] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, 2006.

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通道截面形狀對多晶矽奈米線非揮發性記憶體元件操作特性影響之研究

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