鐵電層負電容場效電晶體之模擬與特性分析

Simulation and Electrical Characteristics of Ferroelectric Negative Capacitance Field Effect Transistors

賴德全(Der-Chuan Lai)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.10198

摘要

隨著摩爾定律持續將元件微縮化，降低邏輯元件的操作功率是必要的；縮小元件的操作電壓為達成此目的的有效手段。在不降低元件的導通啟動電流與不提升漏電流的前提下，欲降低元件的操作電壓，須縮小元件的次臨界斜率。然而傳統電晶體在次臨界斜率上有最小極值的限制，即使將元件次臨界斜率減低至此極值，仍不足以滿足未來更小尺度元件微縮對次臨界斜率的要求；因此，陡峭次臨界斜率元件的研究，即為當前重要的研究議題。
鐵電層負電容電晶體為近期提出的新穎陡峭次臨界斜率元件，其它陡峭次臨界斜率元件像是穿隧式場效電晶體、奈米微機電元件及衝擊游離式場效電晶體，皆分別面臨操作電流過低、反應時間過長以及操作電壓過大與可靠度的問題。傳統鐵電層負電容電晶體的不足之處，在於追求陡峭次臨界斜率時可能產生電流曲線的遲滯效應。
本論文中，我們探討鐵電層負電容的成因與它對元件電性的影響，建立鐵電層負電容電晶體的電性模擬，並提出二個新型鐵電層負電容電晶體結構，以改善傳統負電容電晶體追求陡峭次臨界斜率時出現電流遲滯曲線的缺點。

關鍵字

鐵電層 ； 負電容 ； 次臨界斜率 ； 遲滯曲線

並列摘要

Transistor scaling down has been the principal factor in driving CMOSFET performance improvement for more than thirty years. As transistor scales down, reduction of dynamic switching power (fCVDD2) is required, in concern of power consumption and heat dissipation issue. Transistor operating frequency and capacitance cannot be lowered, in pursuit of higher speed and on current. Therefore, lowering Vdd is the solution to reduce the dynamic switching power as technology nodes progress.
In transistor design, IOFF should remain the same or become even lower to maintain low static power (IOFFVDD), and ION shouldn’t be lower for the sake of delay. As a result, devices with steep subthreshold slopes are desired. However, traditional transistor subthreshold slope is limited at 60 mV/decade due to its thermionic emission transport mechanism. To break through the limit, steep-slope devices with subthreshold slope smaller than 60 mV/decade are required.
Candidates of steep-slope devices include Negative Capacitance FET (NCFET), Tunneling FET (TFET), Nanoelectromechanical relay (NEM relay), and Impact-ionization MOS (IMOS). While TFET suffers from low on current, IMOS suffers from high operating voltage and reliability issue due to its breakdown transport mechanism, and NEM relay suffers from large hysteresis loop and low speed on switching. NCFET stands to be the promising steep-slope device among the candidates. Though traditional NCFET may have hysteresis loop in seek of steep SS, the hysteresis loop can still be eliminated by some novel structure designs of NCFET proposed in the thesis.

並列關鍵字

ferroelectric material ； negative capacitance ； subthreshold slope ； hysteresis

參考文獻

[1] Moore, G.E., Cramming more components onto integrated circuits (Reprinted from Electronics, pg 114-117, April 19, 1965). Proceedings of the IEEE, 1998. 86(1): p.82-85

[2] C. Auth, C.A., A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, , et al. A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors in VLSI 2012.

[4] Kittel, Charles, Introduction to Solid State Physics, 7th Ed., Wiley, 1996

[5] Richard P Feynman, Robert B Leighton, Matthew L Sands, Feynman Lectures on Physics Complete Volumes 2, p.134

[6] Salvatore, G., Bouvet, D., & Ionescu, A. M. (2008, December). Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P (VDF-TrFE)/SiO 2 gate stack. In Electron Devices Meeting, 2008. IEEE International (pp. 1-4)