探討TSV對substrate coupling的影響

范姜毅

指導教授 ： 龔正

國立清華大學/電機資訊學院/電子工程研究所/碩士(2008年)

摘要

Abstract

In this thesis, the substrate coupling is discussed. The most important discussion of substrate coupling is adding TSV (Through-Silicon-Vias), which is proposed to solve the interconnect problem, to suppress substrate coupling. In order to understand the substrate coupling, different conditions are considered such as substrate concentration, substrate thickness, deep trench, the distance, metal shielding, and TSV. The Scattering parameter is used to evaluate the level of substrate coupling and the range of simulation frequency is from 107Hz to 1011Hz. We find that TSV with ground indeed suppress the substrate coupling and show the improvement of 8.3db at 109Hz and 17.3db at 1010 Hz. Therefore, TSV is really a good technique for suppressing substrate coupling.

關鍵字

基板耦合 ； 三維電路

並列摘要

摘要

在這篇論文，主要是探討影響基板耦合的因素，其中最重要的是要探討TSV對基板耦合的影響。TSV是為了解決未來電路連接會產生問題所提出的解決方法，有關TSV的製程會在論文中介紹。除了探討TSV，我們還會探討各種影響基板耦合的因素，包括不同基板濃度，基板厚度，發射端與接收端的距離，加入deep trench，TSV和金屬等。我們是利用S參數來判定基板耦合的難易程度，而程式模擬的頻率範圍是從107Hz到1011Hz。由模擬程式發現接地的TSV可以大大降低基板耦合量。接地的TSV分別可在109Hz 提供8.3dB和1010 Hz 提供17.3dB，因此，接地的TSV是個良好的抑制基板耦合的技巧。

並列關鍵字

TSV（through-silicon-vias） ； substrate coupling

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