下世代先進DRAM堆疊電容─結構/電容分析與設計

隨著記憶體容量增加，製程不斷微縮，每記憶單元(Memory Cell)必須提升電容量並防止電容傾倒接觸短路而失效(Twin Bit Failure)，才能符合下世代先進DRAM之需求。本論文旨在針對DRAM堆疊電容之結構強度和電容量進行分析，並評估其縱剖面及橫截面相關幾何參數之影響，進而藉以設計新式堆疊電容。本論文首先探討X公司無支撐堆疊電容之製程，進行製程溫度效應與可容許偏移量之分析，並計算其電容量。模擬及計算結果顯示：(1) 在現有製程溫度和可容許偏移量下，X公司無支撐堆疊電容之結構強度尚屬足夠；(2) 當該無支撐電容之橢圓截面長短軸比值a/b越大，電容量越大，但在與方向之結構強度則較圓形截面弱；(3) 介電層填實高度越高，偏移量雖越小，但電容量卻會大幅減小；及(4) 若欲避免無支撐電容傾倒接觸，且能增加電容量，經參數分析，可以增加複晶矽(Poly Si)層外徑、加大半球型矽晶粒(Hemispherical Grained Silicon, HSG)層內徑或使電容頂端適度向外傾斜等方式獲得。以上述成果為基礎，吾人進一步設計數種新堆疊電容結構，並進行專利申請。新設計不僅能維持足夠之電容量，防止電容傾倒接觸短路，與習知技術(Prior Arts)相較，更因製程步驟簡單，可有效降低成本，極具產業應用價值。

關鍵字

動態隨機存取記憶體；堆疊電容；電容量；製程分析

並列摘要

In order to meet the requirement of the next-generation DRAM technology for higher density memories, the capacitance per memory cell needs to be increased and the storage node should be prevented from twin bit failure. The objective of this work is to estimate the structural strength and the capacitance of the DRAM stack capacitor, execute the parametric analyses of the capacitor’s profile and cross section and, then, design new stack capacitor. First, this work deals with the manufacturing process of X company's stack capacitor without support, the analyses of manufacturing thermal effect and allowable lateral displacement, and the calculation of the capacitance. The results show that (1) the structural strength of the X company's stack capacitor without support should be safe under the present manufacturing temperatures and allowable lateral displacement; (2) the bigger ratio of major/minor axes of the elliptical cross section of the capacitor without support is, the higher the capacitance it has. However, the structural strength in and directions is weaker than that of the capacitor with circular cross section; (3) with the increase of the height of dielectric layer, the lateral displacement of the capacitor and capacitance decrease; (4) to prevent the collapse contact of the capacitor without support and increase the capacitance, from the parametric analyses, one can increase the Poly Si outer radius, HSG inner radius and/or enlarge the top width of the capacitor. Based on the results described above, several new stack capacitor designs are proposed in this work and the application for patents is in process. The new capacitors can not only provide enough capacitance for data storage, but also keep themselves from twin bit failure. Furthermore, as compared with the prior arts, the new ones have simpler manufacturing process which provides lower cost and have more potential in industry applications.

並列關鍵字

DRAM ； Stack Capacitor ； Capacitance ； Manufacturing Process Analysis

參考文獻

1. Adler, E., DeBrosse, J. K., Geissler, S. F., Holmes, S. J., Jaffe, M. D., Johnson, J.B., Koburger Ill, C. W., Lasky, J. B., Lloyd, B., Miles, G. L., Nakos, J. S., Noble, Jr., W. P., Voldman, S. H., Armacost, M., Ferguson, R., “The evolution of IBM CMOS DRAM technology,” IBM J. Res. Develop., Vol. 39, No. 1/2, Jan./Mar., 1995.

2. Aoki, M., Ozaki, T., Yamada, T., Kawaguchiya, H., Ishibashi, Y., Hamamoto, T., “Fully Self-Aligned 6F2 Cell Technology for Low Cost 1 Gb DRAM,” Toshiba ULSI Res. Lab.,1996

5. Lee, J., Ahn, Y., Park, Y., Kim, M., Lee, D., Lee, K., Cho, C., Chung, T., Kim, K., “Robust Memory Cell Capacitor using Multi-Stack Storage Node for High Performance in 90nm Technology and Beyond,” Samsung Electronics Co., 2003

8. Kim, Kinam, “Perspectives on giga-bit scaled DRAM technology generation,” Microelectronic Reliability, Vol.40, pp.191-206, 2000.

9. Kim, W.D., Joo, J.H., Jeong, Y.K., Won, S.J., Park, S.Y., Lee,S.C., Yoo, C.Y., Kim, S.T., Moon, J.T., “Development of CVD-Ru/Ta2O5/CVD-Ru Capacitor with Concave Structure for Multigigabit-scale DRAM Generation,” IEDM, pp 01-263, 2001.

國際替代計量

下世代先進DRAM堆疊電容─結構/電容分析與設計

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