應用於10Gb/s之高效能矽鍺限幅放大器設計

The Design of High Performance SiGe Limiting Amplifier for 10Gb/s Application

劉秉澄(Ping-Cheng Liu)

指導教授 ： 徐永珍

國立清華大學/電機資訊學院/電子工程研究所/碩士(2007年)

https://doi.org/10.6843/NTHU.2007.00373

摘要

近年來隨著科技之進步，人們對於高速資料傳輸逐漸重視且需要，光纖通訊提供高頻寬介面的性質而沒有電訊號傳輸介面的許多
缺點，所以光纖通訊系統扮演者重要的角色。然而目前在無論學術
界或是產業界，在光纖通訊接收器中將Photo Detector和TIA/LA電
路整合在同一晶片上仍然有許多的問題，其中最大的挑戰為電路頻
寬的限制，若要有較大的光電流輸出則勢必要加大photo detector
的面積，則photo detector的寄生電容也會隨之加大，直接影響到
了整個光纖接收器的頻寬，所以目前光纖接收器大多是經由多個模
組所組成，而photo detector也以III-V族元件居多，成本也相對提高很多。
此次設計一個應用於10Gb/s全整合型光纖接收器，利用SiGe HBT有優於CMOS之光電效應，可以使photo detector的面積最小化，則
寄生電容可以降低，其本身亦具有相當高的fT，很適用來設計高速
電路，所以希望以相較於III-V族或0.18um CMOS便宜之TSMC 0.35μm SiGe BiCMOS 3P3M製程來達到10Gb/s高速、高整合性和高資料量
的整合型光纖接收器。
本論文設計之全整合型光纖接收器，整合了光感測器(PD)、轉阻放大器(TIA)、限幅放大器(LA)。整體的設計，由模擬結果(post-sim，Corner:TT)可得到118.284dBΩ的轉換增益(Conversion Gain)，9.9GHz的3dB頻寬，低頻截止頻率為78KHz，差動輸出振幅為1275mV，data jitter為5ps，電路總共消耗78.16mA的電流。限幅放大器(LA)部分，由模擬結果(post-sim，Corner:TT)可得到63dB的增益，14.5GHz的3dB頻寬，電路總共消耗54.12mA的電流。

關鍵字

限幅放大器

並列摘要

Along with the improvement of technology, people start to realize the importance and need of high data rate transfer, the Optical Fiber Communication provides the property of high bandwidth interface and has no weakness of Electric Telecommunications interface, and therefore, the Optical Fiber Communication System plays an important role for the public nowadays.
However, at present, integrated Photo Detector and TIA/LA into the same chip from Optical receivers still have many problems no matter for the academia or technology industry. Among them, the biggest challenge is the limited by the bandwidth. If we want to have larger photo current, then we certainly need to aggrandize the area of the photo detector, meanwhile, the parasitic capacitance of the photo detector will become larger, and directly influence the bandwidth of whole optical receiver. Because currently most optical receivers are formed with several modules, and the photo detectors are mostly using III-V group compound as the main component, there’s no doubt that the cost raised a lot.
This paper describes the design of a fully integrated 10Gb/s optical receiver, use the optoelectronic property of SiGe HBT, which is better than CMOS, can minimum the area of the photo detector, then parasitic capacitance can reduce ,it also has rather high , very proper for designing high-speed circuit. Consequently, this paper uses TSMC 0.35μm SiGe BiCMOS 3P3M process, which is cheaper than III-V group compound and 0.18 um CMOS to implement a fully integrated 10Gb/s optical receiver with high speed, high integration and high data rate.
The design is a fully integrated optic receiver with PD, TIA and LA. The result of the receiver post-simulation provides a conversion gain of 118.284dBΩ and a 3 dB bandwidth of the 9.9 GHzs. The low-frequency cutoff is 78 KHz, the differential voltage swing is 1275 mV, data jitter is 5 ps .Total current consumption is 78.16 mA . The result of the Limiting amplifier post-simulation provides a gain of 63dB and a 3 dB bandwidth of the 14.5 GHz. Total current consumption is 54.12 mA .

並列關鍵字

Limiting Amplifier

參考文獻

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