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  • 學位論文

應用於10 Gb/s光通接收器之無被動電感前端放大器設計

Design of an Inductorless Front-End Amplifier for 10 Gb/s Optical Receiver in 0.18um CMOS Process

指導教授 : 徐永珍
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摘要


由於科技的進步,大眾對於高速資料傳輸的需求逐漸提高。使用有線介面傳輸,訊號會受到傳輸介質的影響,使原先的訊號受到衰減。將傳輸介質替換成光纖,可提供高頻寬且低雜訊的優點,因此近年來短距離光纖通訊系統在資料傳輸上扮演很重要的角色。 光通接收器在整合上會遇到一些問題,其中最大的挑戰為電路頻寬的限制,若要有較大的光電流輸出勢必要加大光感測器(Photo Diode, PD)的面積大小,故PD的寄生電容也會隨之加大,將直接影響到接收器的頻寬。 本論文利用TSMC 0.18m CMOS製程下實現10Gb/s光通接收器之無被動電感前端放大器的設計,在PD的寄生電容為1pF下,整合了轉阻放大器(Transimpedance Amplifier, TIA)以及限幅放大器(Limiting Amplifier, LA)。在此次設計的電路中使用電壓-電流回授、主動電感以及主動回授電路來拓寬頻寬,並使用內部主動回授來使極點分離,此一方法可以使頻譜平坦化。本次設計亦將差動主動米勒電容(Differential Active Miller capacitor, DMAC)來取代外接式電容,有效減小晶片面積且可避免晶片外部雜訊的干擾。

並列摘要


Due to the progress in technology, high-speed data transmission is highly demanded. In the traditional wire communication, the signal suffers high loss from transmission medium as the data-rate increases. However, replacing the traditional transmission medium by optical fiber provide the advantage of wide bandwidth and low noise. Therefore, short-distance optical communication plays a major role in high-speed data transmission. Among the problems about fully integration of optical receiver on a single chip, one of the difficult challenges is the limit of bandwidth due to the size of photodetector. To increase photocurrent makes the size of the photodiode (PD) larger. However, the parasitic capacitance of the PD will become larger and directly affect the bandwidth of the whole optical receiver. This thesis proposes an inductorless front-end amplifier, fabricated in TSMC 0.18 m CMOS technology, for 10 Gb/s optical receiver under the condition of 1 pF parasitic capacitance of the PD. The chip integrates a transimpedance amplifier (TIA) and a limiting amplifier (LA). By employing shunt-shunt feedback, active inductor, and active feedback, this work broadens the bandwidth. Besides, the interleaving feedback in the circuit not only splits the poles but also make the frequency response flat. Conventional off-chip capacitors are replaced by differential active Miller capacitors (DAMC) in this work in order to achieve an area-efficient design and to avoid off-chip noise.

參考文獻


[3]劉秉澄,應用於10Gb/s之高效能矽鍺限幅放大器設計,碩士論文,清華大學,新竹,2007。
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[8]L.Chen, Z.Li , and Z. Wang, “A 10-Gb/s 0.18-um CMOS optical receiver front end amplifier,” Proc. Asia-Pacific Conf. on Comm., pp. 601-604, 2009

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