一個低面積高輸出效能之多協定影像轉換使用共同因子分散式算術技術

A Low Cost High Throughput Architecture for Multi-standard Video Transforms Using Common Sharing Distributed Arithmetic

陳俊能(Jyun-Neng Chen)

指導教授 ： 張慶元

國立清華大學/電機資訊學院/電機工程學系/碩士(2011年)

https://doi.org/10.6843/NTHU.2011.00567

摘要

影像壓縮標準諸如MPEG-1/2/4、H.264和VC-1是廣泛使用在影像/視訊應用中。在本論文中，提出一個低面積高輸出效能之多協定影像轉換使用共同因子分散式算術(Common sharing distributed arithmetic
，簡稱CSDA)技術可以支援目前較常見影像壓縮標準，並且可以處理四種轉換型態，包含8×8、4×4、4×8和8×8等矩陣轉換。在本論文中，提出的共同因子分散式算術策略可以增加各個影像標準轉換係數(coefficient)間電路共用之能力，並且減少樹狀加法器(adder tree
)之加法數目。因此，提出的二維(2-D)架構只需使用較少的硬體面積來實現。在資料處理上，使用8條平行路徑(paths)且最大操作頻率為205MHz。因此，本論文所提出的二維轉換架構可以達到每秒處理1.64G的像素值(pixels)，而且所需面積為30K邏輯閘(logic gates)
，由於本論文所提出之架構擁有高輸出率(high throughput rate)，因此可以支援數位電影(digital cinema, 4298×2048@24Hz) 4:4:4的亮度色彩比和高畫質電視1080p(high definition television，簡稱HDTV, 1920×1080@60Hz) 4:2:0的亮度色彩比之規格。在技術上，本論文所提出之二維架構使用TSMC 0.18-µm CMOS 1P6M來實現。

關鍵字

多協定影像轉換 ； 分散式算術技術 ； 共同因子分散式算術技術

並列摘要

Video and image compression standards, such as MPEG-1/2/4, H.264, and VC-1, are widely used in video and image
applications. In this thesis, the proposed low cost high
throughput architecture for multi-standard transform using common sharing distributed arithmetic (CSDA) can support variable video compression standards. Moreover, the proposed
architecture can process four transform types including 8 × 8, 4 × 4, 4 × 8,and 8 × 4 transforms. In this thesis, the proposed CSDA strategy can increase the circuit sharing capability among the coecients and reduce the number of adders in adder tree. Hence, the proposed architecture can be implemented by using less hardware cost. In data processing rate, the proposed architecture can process the eight pixel data per cycle and operates in 205MHz clock frequency. Therefore, the proposed two-dimensional (2-D) architecture can achieve 1.64G-pixels/s throughput rate with the hardware cost of 30K gates, and the throughput rate can meet the specications of digital cinema (4298 × 2048@24Hz) with 4:4:4 video processing bits and high denition television (HDTV) 1080p(1920 × 1080@60Hz) with 4:2:0 video processing bits. For verication, the proposed 2-D
architecture is implemented by using TSMC 0.18-m CMOS 1P6M process.

並列關鍵字

Multi-standard video transforms ； Distributed arithmetic ； Common sharing distributed arithmetic

參考文獻

[1] Moving Picture Experts Group Web site,

[2] International Telecommunication Union Telecommunication Standardization Sector Web site, http://www.itu.int/ITU-T.

[3] Offcial Windows Media Web site,

[4] Video Compression standardsWeb site,

http://en.wikipedia.org/wiki/Video compression.