在三維多核心積體電路的架構下透過動態電壓頻率調整技術設計能量有效率利用任務排程

Energy-Efficient Task Scheduling for DVFS-Multi-Core 3D IC

吳丞彬(Cheng-Bing Wu)

指導教授 ： 林永隆

國立清華大學/電機資訊學院/資訊工程學系/碩士(2010年)

摘要

對於未來高效能運算而言，能量有效率利用是很重要的。過度的能量消耗會產生嚴重的熱問題，這不僅會影響系統的可靠度，同時也會影響系統的效能。我們藉由動態電壓頻率調整技術，著重在一個從系統階層角度降低整體能量消耗的任務排程。主要針對具有多核心架構的三維積體電路，我們提出了一個具有時間限制的任務排程系統。我們的目標是在給定的條件下，達到能量消耗最小化的任務安排。實驗結果顯示我們的演算法對於能量消耗的最小化是具有顯著效果的。

關鍵字

排程 ； 動態電壓 頻率調整 ； 多核 ； 三維積體電路

並列摘要

Energy-efficiency is important for future high-performance computing. Excessive energy consumption introduces serious thermal problems, which affect not only the system reliability but also the system performance. We focus on an OS-level scheduling to reduce energy consumption via a Dynamic Voltage and Frequency Scaling (DVFS) technique. We proposed a time-constrained task scheduler targeted toward a multi-core 3D IC. Our goal is to minimize the total energy consumption. Experimental results show that our algorithm is effective in energy minimization.

並列關鍵字

scheduling ； DVFS ； multi-core ； 3D IC

參考文獻

[2] Tilera Corporation, http://www.tilera.com.

[4] Y.-K. Kwok and I. Ahmad, “Static scheduling algorithms for allocating directed task graphs to multiprocessors”, ACM Computing Surveys, 1999.

[8] A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. Brodersen, “HYPER-LP: A system for power minimization using architectural transformations”, Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 1992.

[9] T. Ishihara and H. Yasuura, “Voltage scheduling problem for dynamically variable voltage processors”, Proceedings of International Symposium on Low Power Electronics and Design, 1998.

[10] Y. Zhang, X. Hu, and D. Chen, “Task scheduling and voltage selection for energy minimization”, Proceedings of IEEE Design Automation Conference, 2002.