考量多核心系統晶片整合三維堆疊記憶體架構之溫度限制下效能最佳化工作資料擺置設計方法

Thermal-aware Task and Data Placement for Optimizing the Performance of Multi-Processor System-on-Chips with 3D-stacked Memories Architecture

吳承恩(Cheng-En Wu)

指導教授 ： 陳依蓉

國立暨南國際大學/科技學院/資訊工程學系/碩士(2017年)

摘要

利用三維堆疊技術(Three Dimensional Die-Stacking) 將記憶體與多核心系統晶片(Multi-Processor Systems-on-Chips, MPSoCs) 整合於同一晶片，被視為可解決MPSoC 記憶體頻寬(memory bandwidth) 需求問題的方法之一。但三維堆疊的方式也會因為耗能密度的增加，使晶片較常在接近或甚至過熱的情況下執行。由於為避免系統過熱的控溫方法都有不可避免的效能衰退，因此，MPSoC 整合三維堆疊記憶體的主要研究議題之一為如何能控制系統溫度又不傷害系統效能。為達此目的，其中一個方法，是利用系統開發初期，進行考量溫度之軟體架構設計，如資料與工作配置及排程，使系統在動態執行時，能正常全速執行且系統較不易面臨過熱的情況。我們發現過去的方法，都只有利用工作配置，或是資料配置進行系統溫度控制。但我們觀察到，MPSoC 整合三維堆疊記憶體架構之系統最高溫度，來自於各堆疊晶片上的行為，也就是處理器處理軟體工作以及堆疊記憶體的存取都會影響到系統之最高溫度。因此，為達最佳之系統溫度控制，應協力進行資料與工作配置。在此論文中，提出了第一個考量目標架構溫度之資料與工作同時配置設計自動化方法，其目標為在給定之系統溫度限制下，使系統效能達到最佳。我們利用分析應用程式組在執行時的產熱行為，作為工作及資料擺置的依據，我們提出的方法，利用快速的系統溫度與效能預估方法，在系統設計時，進行對系統溫度與效能最有利之工作與資料配置方法的搜尋。實驗結果顯示，與之前只考量效能之資料配置方法相比，我們的方法在符合溫度限制下，系統效能只有10%的損失。與只有利用資料配置進行控溫之方法相比，我們的方法在系統效能方面有5% 之增進，與只有利用工作配置進行進行控溫之方法相比，我們的方法在系統效能方面有5.3% 之增進。

關鍵字

三維堆疊 ； 多核心系統晶片 ； 系統層設計自動化 ； 溫度問題

並列摘要

The architecture of Multi-Processor Systems-on-Chips (MPSoCs) with 3D-stakced memories is considered as one of the most promising way to mitigate the memory wall problem of an MPSoC. However, the increasing power density of a 3D IC makes the MPSoC more likely to be in the thermal emergent condition. Studies also show that, devices that are vertically aligned in the 3D IC have strong thermal correlation, and devices that are farther from the heat sink have more difficulties in thermal dissipation. To ease the thermal emergent problem of an 3D IC, the power consumption of each vertically aligned device should be managed to avoid overheating. The management of power consumption can be achieved by software design techniques, such as thermal-aware task scheduling and data placement, or hardware design techniques, such as allocating SRAM and DRAM layers according to the thermal limit. In this paper, we focus on the design of the software architecture, and propose a thermal-aware task and data placement synergistically method for the target architecture. Different form the existing thermal-aware task scheduling and data placement methods that consider the stacked cores or stacked memories only, the synergistically method designed in this paper considers the heterogeneity of cores and memory elements to optimize system performance given the thermal constraint. In experimental results, compare to performance-aware method, our method only loss 10% system performance below thermal constraint. Compare to data-only placement and task-only placement, our method have respectively improved 5% and 5.3% system performance.

並列關鍵字

Thermal-aware Design ； Task and Data Allocation ； MPSoCs ； 3Dstacked Memories

參考文獻

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