三維堆疊整合處理器與動態隨機存取記憶體晶片之動態散熱管理研究與分析

Analysis of Dynamic Thermal Management in 3D-stacked DRAM-on-processor

陳君維(Chun-Wei Chen)

指導教授 ： 楊佳玲

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.01953

摘要

三維堆疊整合記憶體晶片技術使得記憶體晶片可直接堆疊於微處理器上，因此大大的減少了微處理器和記憶體晶片間的線路延遲時間。許多研究皆已指出憑藉著此種技術，系統的效能將會得到提升。但此種架構因為大幅地增加了功率密度，導致晶片的溫度相比於傳統二維晶片來得高，也使得溫度變成了此種架構上更必須去處理的問題。
動態散熱管理是一種用來控制系統溫度的技術。過去已有許多動態散熱管理技術被提出並用來解決二維晶片系統的過熱問題。然而，三維堆疊整合記憶體晶片帶來的過熱問題會產生多大的影響還是個未知數。並且，三維堆疊整合記憶體晶片在散熱上的特性也使得動態散熱管理的設計變得更複雜。
本論文提出了三維架構下整合效能、功率、溫度模組的模擬器。並實作了多種既存的動態散熱管理機制，對此架構下的散熱問題做初步的探討。

關鍵字

多核心處理器 ； 動態散熱管理 ； 三維整合 ； 溫度分析 ； 隨機記憶體晶片

並列摘要

Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby signi cantly reducing wire delay between the two. Previous studies have examined the performance bene ts of such an approach. However, the high power density makes the thermal issues more critical than 2D does. Dynamic thermal management is a technique to control the temperature of a system. Several DTMs had been proposed to solve the thermal emergency of 2D systems. What are the impacts of thermal issues really have to 3D-stacked DRAMs-on-processor are unknown. And the additional characteristics of 3D-stacked DRAMs-on-processor makes the DTM more complex. In this work, we construct performance, power and thermal model for 3D architecture. And we also perform preliminary studies on DTM policies in 3D architecture via the simulation framework we construct.

並列關鍵字

Chip-multiprocessor ； dynamic thermal management ； 3-D integration ； thermal analysis ； DRAM Memories

參考文獻

[1] B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb. Die stacking (3d) microarchitecture. In Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on, pages 469 {479, dec. 2006.

[3] J. Donald and M. Martonosi. Techniques for multicore thermal management: Classi cation and new exploration. In Computer Architecture, 2006. ISCA '06.

[8] W. Huang, K. Skadron, S. Gurumurthi, R. Ribando, and M. Stan. Di erentiating the roles of ir measurement and simulation for power and temperature-aware design. In Performance Analysis of Systems and Software, 2009. ISPASS 2009. IEEE International Symposium on, pages 1 {10, april 2009.

[11] J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Thermal modeling and management of dram memory systems. SIGARCH Comput. Archit. News, 35(2):312{322, June 2007.

[12] C. Liu, I. Ganusov, M. Burtscher, and S. Tiwari. Bridging the processor-memory performance gap with 3d ic technology. Design Test of Computers, IEEE, 22(6):556 { 564, nov.-dec. 2005.