With the increasing number of embedded memory cores in modern electronic system designs, the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective approach for memory testing. However, memory BIST for three-dimensional integrated circuits (3D ICs) has not been well studied. Different from 2D SOCs, the testing of 3D ICs consists of both pre-bond testing and post-bond testing. Therefore, extra memory BIST controllers may be required for each layer to reduce the total test application time. In this thesis, we propose a two-stage approach: the first stage performs memory grouping under distance constraints and the second stage performs test scheduling under power constraints. Compared to the previous work, our approach can improve both BIST area cost and total test time simultaneously.