適用於三維晶片的時脈同步電路

Die-to-Die Wire-Independent Clock Synchronization for 3D IC

柯智偉(Ji-Wei Ke)

指導教授 ： 黃錫瑜

國立清華大學/電機資訊學院/電機工程學系/碩士(2011年)

https://doi.org/10.6843/NTHU.2011.00699

摘要

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-ADDLL) and a Dual Locking Mechanism, this method can be used to maintain a global clock signal between two dies in a 3D-IC, and thereby enabling the synchronous 3D-IC design methodology. Unlike previous methods, ours does not need to know the delay of the inter-die clock wire.

關鍵字

三維晶片 ； 時脈同步電路

並列摘要

現今製程技術不斷的進步下，有限平面內所能擺放的電晶體個數將因達到各元件所能容忍的最小尺寸而趨於飽和。三維晶片（3D IC）被認為可有效的解決此問題，透過垂直方向堆疊多個平面以增加擺放面積。這些垂直排列且互相平行的平面則是利用一種稱作穿矽孔（Through Silicon Via, TSV）的橋樑來進行彼此間的溝通。
這篇論文提出了一個新式裸晶與裸晶間( die-to-die )且以全標準元件( Fully cell base )實現的時脈校正( clock synchronization )電路與方法，參考之前的論文，我們是第一個提出這樣電路架構的作品，並且電路以標準元件所組成，因此易於轉移到其它製程上，會成為其優勢。

參考文獻

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