一個高效能對H.264/AVC中全文自適應二進制算術解碼器的全硬體架構設計

在H.264/AVC中，全文自適應二進位解碼器有很高的壓縮率，但是複雜度很高，所以我們之前已經提出一個全硬體架構，使它可以支援四倍高清(QFHD)大小的影像且最大碼率80 Mbps，為了支援更高層次的應用，我們分析每種元素(Syntax Element)的位元子(bin)分布以及我們舊有硬體的性能，分析結果顯示mvd元素佔據了所有位元子很大的部份而且Get-Neighbor(GN)程序降低算數引擎(AE)的使用率，所以我們提出了三個方法去改進。對mvd元素我們提出兩位元子算數引擎(TBAE)，它可以在一個循環內解出兩個mvd位元子；為了增加算數引擎(AE)的使用率，提出了兩個方法，第一，藉由平衡最長路徑來減少GN程序的循環數，第二，我們用猜測的方法讓GN和AE能夠平行執行。最後實驗結果顯示我們新的硬體架構有45%的吞吐量改進，而且在238 MHz下可以支援四倍高清大小的影像且最大碼率221 Mbps。

關鍵字

全文自適應二進制算術解碼器； HASH(0x1d3166f0)

並列摘要

Context-based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC can achieve high compression ratio at the expense of high computational complexity. We have previously proposed a fully hardwired CABAC decoder that supports real-time QFHD (4x1080HD) decoding at the maximum bit rate of 80 Mbps. For higher end applications, we analyze the bin distribution of each Syntax Element (SE) type and the performance of our previous work. The analysis results show that mvd SEs account for significant amount of bins and Get-Neighbor (GN) process degrades the utilization of Arithmetic Engine (AE). Therefore, we propose three methods to speed up mvd decoding and increase AE utilization. For mvd SEs, we use a Two-Bin Arithmetic Engine (TBAE) to decode two mvd bins per cycle. To increase AE utilization, we reduce the cycle-count of the GN process by balancing its critical path. In addition, we propose a prediction method to perform AE and GN in parallel. Experimental results show that our new CABAC decoder can achieve 45% throughput (in bins per second) improvement and is capable of real-time decoding QFHD video at the maximum bit rate of 221 Mbps when running at 238 MHz.

並列關鍵字

H.264/AVC ； CABAC Decoder

參考文獻

[2] D. Marpe, H. Schwarz and T. Wiegand, “Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard,” IEEE Transactions on Circuits and Systems for Video Technology, pp. 620-636, July 2003.

[5] J. W. Chen, C. R. Chang and Y. L. Lin, “A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC,” IEEE International Symposium on Circuits and Systems, pp. 4525-4528, May 2005.

[7] W. Yu and Y. He, “A high performance CABAC decoding architecture,” IEEE Transactions on Consumer Electronics, pp. 1352-1359, November 2005.

[8] Y. C. Yang, C. C. Lin, H. C. Chang, C. L Su and J. I. Guo, “A high throughput VLSI architecture design for H.264 context-based adaptive binary arithmetic decoding with look ahead parsing,” IEEE International Conference on Multimedia and Expo, pp. 357-360, July 2006.

[10] Z. Peng, G. Wen, X. Don and D. Wu, “High-performance CABAC engine for H.264/AVC high definition real-time decoding,” IEEE International Conference on Consumer Electronics, pp. 1-2, January 2007.

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一個高效能對H.264/AVC中全文自適應二進制算術解碼器的全硬體架構設計

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