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  • 學位論文

基底雜訊耦合效應對壓控振盪器影響之分析與模型

Analysis and Modeling of the Substrate Noise Coupling Effect in Voltage Controlled Oscillators

指導教授 : 徐碩鴻
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摘要


本論文之重點將在於設計及分析電感電容共振型壓控振盪器,以抵抗高頻基底雜訊耦合效應。文中將以實做使用包括微機電製程(MEMs)、Deep N-well層(DNW)、及特殊形狀金屬接地保護層(PGS)等方式作為電感電容共振型壓控振盪器之電感,做為基底雜訊耦合效應的研究。研究中將使用外部訊號源打入雜訊,以觀察出現在壓控振盪器基頻震盪能量兩側之二階調變及三階調變突波之影響。進一步等效電路模型的建立亦將會包含在本論文中,以解釋觀察到之現象。 首先研究5-7 GHz操作頻率之雙電容開關,並使用微機電製程電感之電感電容共振型壓控振盪器對於基底雜訊之影響。相對於使用標準電感之壓控振盪器,使用微機電製程電感之壓控振盪器擁有約80 MHz之頻飄,壓控振盪器旁之二階調變雜訊突波較標準壓控振盪器設計高約2-3 dBm,但亦可觀察到其三階調變雜訊突波較標準設計低約2-3 dBm。 接著將研究使用DNW與PGS之電感、2.4 GHz操作頻率的電感電容共振型壓控振盪器對於基底雜訊之影響。在相同的壓控振盪器電路基本特性下,使用DNW與PGS電感之電感電容共振型壓控振盪器分別有較標準設計低約6-8 dBm以及8-15 dBm之三階調變雜訊突波,但仍保持相同之二階調變雜訊突波。最後,可利用建立符合物理意義的等效電路模型,以各種不同電感設計在等效電路模型中的差異性,來解釋觀察到的現象。

關鍵字

基底雜訊 壓控震盪器 電感

並列摘要


This study focuses on designing and analyzing the LC voltage-controlled oscillators for high substrate noise coupling immunity. The LC-VCOs with various types of the improved inductors including MEMs inductors, deep N-well (DNW) inductors, and patterned ground shield (PGS) inductors are implemented to investigate the substrate noise coupling effects. The external noise is injected to see the impacts of the proposed designs on the second-order (IM2) and third-order intermodulation (IM3) spurs of the VCOs. In addition, the equivalent circuit models are established to explain the observation trends. First, the substrate noise coupling effects in a 5-7 GHz two-switch LC-VCO using a MEMs inductor are investigated. With a frequency variation around 80 MHz, the IM2 spurs of the VCO with a MEMs inductor are about 2-3 dBm higher than that of the standard design, while smaller IM3 spurs about 2-3 dBm are observed. Then the substrate noise coupling effects in a 2.4 GHz LC-VCO with DNW and PGS inductors are studied. With a similar circuit performance, the IM3 spurs of the VCOs with DNW and PGS inductors are about 6-8 dBm and 8-15 dBm lower than that of the standard design, respectively, but the IM2 spurs are almost unchanged. Finally, physical-based equivalent circuit models are established to explain the observed trends.

參考文獻


[1] S. Wang, Y. Wu, S. Hsu, and C. Chan, “Substrate coupling effect under various noise injection topologies in LC-voltage controlled oscillator,” IEEE RFIC Symp., pp.705-708, Jun. 2007.
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[4] M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, “Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver,” IEEE Custom Integrated Circuits Conf., pp. 353-356, May 2000.
[5] A. Helmy and M. Ismail, “The chip - a design guide for reducing substrate noise coupling in RF applications,” IEEE Circuits & Devices Magazine, pp. 7-21, Sep./Oct. 2006.
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