K頻帶低雜訊放大器、壓控振盪器、四相位壓控振盪器之設計與實現

Design and Implementation of K-Band LNA,VCO,and QVCO in 0.18um CMOS Technology

許安升(An-Sheng Hsu)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2012年)

https://doi.org/10.6837/NCNU.2012.00137

摘要

本論文以TSMC 0.18μm CMOS製程實現射頻前端接收相關電路為目標，操作頻率在3.1~10.6GHz超寬頻頻帶以及K頻帶與12GHz附近，並以設計低雜訊放大器與壓控振盪器為主，研究主題分為四部分:
第一部分為應用在3.1~10.6GHz超寬頻低雜訊放大器，利用台積電0.18μm CMOS 製程來實現。本研究使用一級的inverter加上一級common source的技術來完成此電路，且在第二級common source上使用feedback resistance，以達到寬頻、低雜訊、低功耗且輸入輸出皆匹配。量測結果:在3.1~10.6 GHz的頻帶中S11的耗損皆在-10 dB以下，S22的耗損皆在-9.6 dB以下，在S21的增益方面為10.06±1.3 dB，晶片面積為0.53 mm2，電路功率消耗為13 mW。
第二部分為應用在24GHz短距離雷達系統的寬頻低雜訊放大器，利用台積電0.18μm CMOS 製程來實現。架構有兩種，為了達到較高增益與低功耗，在第二與第三級使用了電流共用技術，第一級為共源級放大器，並使用T型匹配使輸出端匹配達到一個良好的結果，在第一個架構中使用Self-Forward- Body-Bias(SFBB)技術以操作在更低的偏壓下而更降低功耗。量測結果: S11的耗損皆在-8.9dB以下，S22的耗損皆在-9.4dB以下，3dB增益頻寬為7 GHz為20~27 GHz，雜訊為5.56~5.93dB，電路功率消耗為7.77 mW，晶片面積為0.63 mm2; 在第二個架構中，在第四級加上具有回授電阻的共源級放大器，可使增益表現更平坦，模擬結果: S11的耗損皆在-10.1dB以下，S22的耗損皆在-10.1dB以下，3dB增益頻寬為11 GHz為18~29 GHz，雜訊為3.6~3.87dB，電路功率消耗為10.7 mW，晶片面積為0.64 mm2，此結果適合應用於需要高解析度的雷達系統。
在第三部分我們實現了一個低相位雜訊的K頻帶壓控振盪器，利用台積電0.18μm CMOS 製程來實現，在交叉耦和對的基體端加上小電容至地，從模擬結果顯示，在電壓0.8V供應之下可調範圍為25.76 GHz到27.84 GH (2.08 GHz 7.76%)，輸出功率為-1.561±0.105 dBm，最低的相位雜訊為 -120.07 dBc/Hz。
第四部分是利用P型場效電晶體當電流源來達到低電流，來達到低功耗的設計，並且結合交叉偶和對的寄生電容來達到更大的頻率可調的效果，再利用4個電晶體來偶和兩組壓控振盪器來完成四相位輸出，在量測結果來看，在0.72V的電壓下，可調範圍為10.14 GHz 到 11.02 GHz (880 MHz 8.3%)，輸出功率為-8.9±1.92 dBm，在1 MHz的偏移量相位雜訊為 -104.74 dBc/Hz，在功耗方面，單組壓控振盪器的功耗為1.76mW，整體四相位壓控振盪器核心部分的功耗為3.53mW，非常適合用在低功耗系統。

關鍵字

低雜訊放大器 ； 24GHz短距離雷達系統 ； 電流共用 ； SFBB ； 壓控振盪器 ； 四相位

並列摘要

The thesis mainly uses TSMC 0.18μm CMOS process to implement the RF receiver front-end correlative circuits, operating frequency at 3.1~10.6GHz UWB, K-Band, and 12GHz nearby systems, the major designs are low noise amplifier and voltage control oscillator, researchful theme can be divided into four parts：
In the first part, low noise amplifier is applying at 3.1~10.6GHz UWB, using the TSMC 0.18μm CMOS process to implementation. This study uses one stage of the inverter and one stage of the common source to achieve the circuit, and uses feedback resistance at the second stage, which to achieve wideband, low noise figure, low power consumption and has good impedance matching at input and output. The measured results: S11 is lower than -10 dB over 3.1~10.6 GHz and S22 is lower than -9.6 dB over 3.1~10.6 GHz; S21 is 10.06±1.3 dB. The chip area is 0.53 mm2, the power consumption of the circuit is 13 mW.
In the second part, the wideband low noise amplifier is used for a 24 GHz short-range radar system, using TSMC 0.18μm CMOS process to implementation. There are two structures. In order to obtain high gain and low power consumption, it is using current-reuse technique at the second stage and the third stage. The first stage is common source amplifiers, and use T-matching to achieve good result of output matching. It uses Self-Forward-Body-Bias(SFBB) technique in the first structure to operate at lower voltage and lower the power consumption. The measured results: S11 is lower than -8.9 dB and S22 is lower than -9.4 dB. The 3-dB gain bandwidth is 7GHz from 20~27GHz. The noise figure is 5.56~5.93dB. The power consumption of the circuit is 7.77 mW and chip area is 0.63 mm2. In the second structure, adding a common source amplifier with feedback resistance to flatter gain performance. The simulation results: S11 is lower than -10.1 dB and S22 is lower than -10.1 dB. The 3-dB gain bandwidth is 11GHz from 18~29GHz. The noise figure is 3.6~3.87dB. The power consumption of the circuit is 10.7 mW and chip area is 0.64 mm2. The results show that the LNAs are suitable for high resolution radar systems.
In the third part, we achieved a low phase noise K-Band VCO using TSMC 0.18μm CMOS process. We connected a small capacitance to the ground in cross-coupled pair’s body. The simulation results: when the power supply voltage is 0.8V, the tunning range is 25.76 GHz to 27.84 GH (2.08 GHz 7.76%). The output power is -1.561±0.105 dBm and the lowest phase noiste at 1 MHz offset is -120.07 dBc/Hz.
The fourth part, it is using the PMOS as current source to achieve low current and low power consumption in this design, and combined the intrinsic-tuned technique to achieve wider tunning range and use four NMOS to couple the signal of two VCO and realize the quadrature signal. The measured result : when the power supply voltage is 0.72V, the tunning range is 10.14 GHz to 11.02 GHz (880 MHz 8.3%). The output power is -8.9±1.92 dBm and the phase noise at 1 MHz offset is -104.74 dBc/Hz. The power consumption of the VCO and QVCO are 1.76mW and 3.53mW. This is very suitable for low power system.

並列關鍵字

low noise amplifier ； 24 GHz short-range radar system ； front-end ； current- reuse ； SFBB ； voltage control oscillator ； quadrature

參考文獻

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