應用於MOS元件封裝應力影響評估的時序控制電路設計與實現

Sequence Controlled Circuit Design And Implementation for Evaluating the Effect of Package Stress on MOS Devices

黃啟□(Chi-Heng Huang)

指導教授 ： 龔正

國立清華大學/電機資訊學院/電子工程研究所/碩士(2008年)

摘要

本論文採用一個經過改良的時序控制電路來設計MOS電晶體的量測電路，利用位移暫存器與傳輸閘的特性，來做MOS元件特性的量測，並使用kelvin式的量測方式來解決傳輸線的電壓降問題。在整個設計的MOS參數中，考慮了NMOS與PMOS電晶體的不同寬度與長度以及LOD（Length of Diffusion）[1]長度，且只使用了13個量測PADS，總面積為600umX500um。此一電路放置在晶片的不同位置以觀察其在不同位置上所受應力不同而使元件產生的變化。本設計與實驗的目地是用來研究一個MOS電晶體在晶圓製作完成後到封裝完成後，因所受應力不同而產生的特性漂移。所使用的是目前主流的先進製程，65nm的低秏電邏輯CMOS製程；封裝則採用覆晶Flip-Chip技術。

關鍵字

應力 ； 控制電路 ； 封裝

並列摘要

An improved sequencial controlled circuit is designed and implemented to measure the package stress effect on MOS transistors. It employs the characteristics of shift register and transmission gate to measure the characteristics of MOS devices. For resolving the issue of voltage drop due to routing, it utilizes the Kelvin measurement. The transistors under test include NMOSFETs and PMOSFETs, both with different channel widths and lengths, also included is LOD (Length of Diffusion). This circuit has only 13 probing pads and the total area for each measured circuit is 600um×500um. The measured circuits are placed in different locations within the chip for observing the stress effect in different locations. The purpose of the experiment is to research the MOS transistors’ characteristics change before and after package process. The silicon process is the mainstream 65nm low power logic CMOS process and the package type adoped is Flip-Chip packaging.

並列關鍵字

MOS ； HASH(0x1d73e220) ； HASH(0x1d73e2c0)

參考文獻

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