摘要
隨著半導體製程的進步，無線通訊系統頻段也逐漸地升高，在通訊系統收發器中本地振盪器輸出頻率也隨之提高，本論文提出一個在ISM頻段使用，中心頻率為60 GHz，可調範圍57~64 GHz的寬調變範圍鎖像迴路。 第二章開始介紹鎖相迴路基本操作原理，並針對迴路中子電路做逐一介紹，推倒迴路轉移函數和相位雜訊數學模型。 第三章為本論文所提出之57~64 GHz的寬調變範圍鎖像迴路架構，首先對所提出架構之迴路參數利用Matlab做模擬驗證，包含相位邊限、雜訊分析、迴路鎖定模擬，並針對鎖相迴路中各區塊的電路架構做介紹，輸入參考頻率為25 MHz，在充電泵電流、壓控振盪器、注入式鎖定除頻器皆具有可調作用，使鎖相迴路具備有寬頻的作用，並對壓控振盪器、注入式鎖定除頻器之頻率調變原理加以說明，接著並探討說明迴路行為中的非理想現象並且設法加以改善，以提升鎖相迴路的效能。 第四章著重於電路架構的模擬，分別對單一區塊做模擬驗證外，也對整個鎖相迴路做系統的模擬，包含迴路鎖定、相位雜訊模擬；本次使用的為台積電65nm製程下線，最後附上電路佈局圖做說明。
並列摘要
With the advances in semiconductor process, the band of the wireless communication system gradually increased, the local oscillator output frequency in the transceiver of the communication system also will improve, This paper presents a center frequency of 60 GHz in the ISM band, 57 ~ 64 GHz wide tuning range lock loop. The second chapter introduces the basic operation of the phase-locked loop principle, neutron circuit for the circuit one by one, the tear down the loop transfer function and phase noise of mathematical models. Chapter three of this paper of 57 to 64 GHz wide tuning range lock like a loop structure, the first on the circuit parameters of the proposed framework using Matlab to do simulation and verification, including the phase margin, noise analysis, the loop is locked analog, and for each block in the phase-locked loop circuit architecture, the input reference frequency of 25 MHz in the charge pump current, VCO, injection locked frequency divider are adjustable role of phase-locked loop with broadband the role of the voltage-controlled oscillator injection locking in addition to the frequency of the frequency modulation principle described, then explore and explain the phenomenon of non-ideal circuit behavior and seek to improve to enhance the performance of phase-locked loop. The fourth chapter concerns focus on the circuit structure of the simulation, the simulation and verification of a single block, the entire phase-locked loop to do the simulation, including the loop is locked, the phase noise simulation; use TSMC 65nm process off the assembly line, and finally attached to the circuit layout illustration.
參考文獻
延伸閱讀
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