一個快速鎖定460.1MHz至6.177GHz之全數位式鎖相迴路的設計

Design of a Fast-Locking 460.1MHz to 6.177GHz All-Digital Phase Locked Loop

陳逸瑋(Yi-Wei Chen)

指導教授 ： 洪浩喬

國立交通大學/電機學院/電機與控制工程系所/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00295

摘要

本論文提出了一個可快速鎖定與寬幅調整之全數位式鎖相迴路的設計。在鎖定方式的部分，為了達到快速鎖定的目的，我們將鎖相迴路分為頻率捕捉與相位追蹤兩模式。在頻率捕捉模式下使用了名為Regula Falsi的方式來預測輸出頻率，並且不論數位控制振盪器的線性與否，此方法保證鎖相迴路的頻率一定可以鎖定；在相位追蹤模式則使用了兩種不同的迴路頻寬大小來進行相位鎖定與抖動抑制，第一階段使用較大迴路頻寬來快速的追蹤相位鎖定軌跡，第二階段則使用較小的頻寬，其目的在於降低鎖定後的相位雜訊及抖動。
　　本電路已經使用TSMC 90nm CMOS的技術實現，核心面積為0.0646 mm2，而整體晶片面積為0.709 mm2。量測結果顯示頻率部分的鎖定時間為5個參考頻率週期，而相位鎖定的部分則只需3個週期即可完成；鎖相迴路輸出頻率的範圍則為460.1 MHz至6.177 GHz，而峰對峰抖動值的表現部分，在480 MHz的輸出頻率時為1.9% U.I.，在3 GHz的輸出頻率可達到11.7% U.I.，在5 GHz的輸出頻率可達到7.0% U.I.，而在6 GHz的輸出頻率則為5.1% U.I.；在輸出頻率為6 GHz下，相位雜訊為-81.68 dBc/Hz@1MHz與-108.22 dBc/Hz@10MHz。此全數位式鎖相迴路的功率消耗效率為9.2370 mW/GHz。

關鍵字

全數位式鎖相迴路 ； 快速鎖定 ； 寬幅調整 ； 錯位法

並列摘要

This thesis presents a design of fast-locking and wide-range all-digital phase locked loop (ADPLL). The locking procedure is partitioned into two modes including the Frequency Acquisition mode and the Phase Tracking mode. In the Frequency Acquisition mode, a novel frequency locking method called Regula Falsi is used for faster frequency locking. No matter the transfer curve of the digitally controlled oscillator (DCO) is linear or not, the method guarantees the frequency can always be locked. In addition, the frequency can be locked within two steps if the DCO has a linear transfer function. In the Phase Tracking mode, the ADPLL adopts two different loop bandwidths. The design first issues a wider loop bandwidth to speed up the phase tracking. After the phase is locked, the loop bandwidth is adjusted to a smaller one to reduce the phase noise and jitter.
The circuit has been implemented in TSMC 90nm CMOS technology. The core area is 0.0646 mm2 and the whole chip area with bonding pads is 0.709 mm2. Measurement results show that the lock-in time of frequency takes 5 cycles and the lock-in time of phase is 3 cycles. The output frequency range is from 460.1 MHz to 6.177 GHz. The pk-pk jitter at 480 MHz output is 1.9% U.I., at 3 GHz output is 11.7% U.I., at 5 GHz output is 7.0% U.I., and at 6 GHz output is 5.1% U.I. Under the 6 GHz output frequency, the phase noise at 1 MHz offset is -81.68 dBc/Hz and at 10 MHz offset is -108.22 dBc/Hz. The ADPLL achieves a power efficiency of 9.2370 mW/GHz.

並列關鍵字

ADPLL ； Fast Locking ； Wide Tuning Range ； Regula Falsi

參考文獻

[4] D. W. Boerstler, “A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 513-519, 1999.

[5] B.-J. Lee, M.-S. Hwang, S.-H. Lee, and D.-K. Jeong, “A 2.5-10-Gb/s CMOS Transceiver With Alternating Edge-Sampling Phase Detection for Loop Characteristic Stabilization,” IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1821-1829, 2003.

[6] F. G. Agis, C. Ware, D. Erasme, R. Ricken, V. Quiring, and W. Sohler, “10-GHz Clock Recovery Using an Optoelectronic Phase-Locked Loop Based on Three-Wave Mixing in Periodically Poled Lithium Niobate,” IEEE Photonics Technology Letters, vol. 18, no. 13, pp. 1460-1462, 2006.

[7] A. W. L. Ng, G. C. T. Leung, K.-C. Kwok, L. L. K. Leung, and H. C. Luong, “A 1-V 24-GHz 17.5-mW Phase-Locked Loop in a 0.18-um CMOS Process,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1236-1244, 2006.

[9] J. Kim, J.-K. Kim, B.-J. Lee, N. Kim, D.-K. Jeong, and W. Kim, “A 20-GHz Phase-Locked Loop for 40-Gb/s Serializing Transmitter in 0.13-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 899-908, 2006.