應用於液晶顯示器源驅動器之具備掃描式解碼器的八位元數位類比轉換器

An 8-Bit Compact Digital to Analog Converter with Scanning Decoders for TFT-LCD Source Driver ICs

王威傑(Wang, Wei Chieh)

指導教授 ： 盧志文

國立清華大學/原子科學院/工程與系統科學系/碩士(2012年)

摘要

這篇論文提出了一應用於液晶顯示器之源驅動器之具備掃描式解碼器的八位元數位類比轉換器。現今由於市場的需求，液晶顯示器朝著大型化，高解析度的趨勢發展。尤其是行驅動器裡的數位類比轉換器，如何滿足大型化，高解析度的需求，卻能夠減少整個行驅動器的面積達到減少成本的目的，一直是行驅動器設計重要規格之一，具備掃描式解碼器的數位類比轉換器，比傳統的數位類比轉換器還更省面積，傳統液晶顯示器之行驅動器的數位類比轉換器是由一組電組串做分壓在經過各個通道的解碼器去選至對應到資料的電壓值去做色彩顯示。具備掃描式解碼器的數位類比轉換器是應用二階開關去做循序式的選擇電壓，當選到電壓會停止繼續打開開關然後選擇電壓，選到的電壓會經過開關送到輸出緩衝器，再送到面板上提供液晶不同的扭轉率顯示色彩。利用二階開關取代解碼器，對於需要很多通道的行驅動器來說，特別是高解析度行驅動器，更可以省下不少面積。
本研究使用TSMC 0.35μm 2P4M技術設計並且完成晶片研製，此晶片是八位元數位類比轉換器且擁有八個通道，DNL/INL最差是0.32/0.37LSB，輸出緩衝器穩定時間是4.5us，單一通道面積是0.0014mm2，八位元二階漸進式數位類比轉換器面積只有傳統數位類比轉換器面積的27%

關鍵字

二階漸進式數位類比轉換器 ； 選擇控制電路 ； 行驅動器

並列摘要

In the thesis, an 8-bit compact digital to analog converter for TFT-LCD source driver ICs with scanning decoders is purposed. Currently, the requirement of LCD market is toward to large size, high resolution development. Especially the digital to analog converter (DAC) of column driver ICs, how to arrive requirement of large size and high resolution but will achieve purposed of reducing area are always the important specifications. DAC with scanning decoders costs less area than conventional DAC. The conventional DAC for LCD column driver ICs makes use of a resistor string dividing voltage, after that, going through each channel of decoder to select the voltage of corresponding data to show the color. DAC with scanning decoders makes use of the two stage switches to select the voltage sequentially. When the voltage corresponding to the data being selected, the switches will stop sequentially turn on switches and the buffer output will arrive the voltage corresponding to the data, after that, giving the liquid crystal different twist angle to show the color on display. As column driver ICs in need of many channels as concerned, taking advantage of second stage switches instead of decoders especially for the high resolution column driver will cost many areas down.
This research prototype was realized in TSMC 0.35μm 2P4M technology. This chip is 8 bit DAC for 8 channels with the worst DNL/INL of 0.32/0.37 LSB. The settling time of the output buffer spends 4.5us. The area of each channel is 0.014mm2, which occupies only 27 % of the conventional 8-bit RDAC area.

並列關鍵字

two stage sequential DAC, ； pick out control circuit ； column driver

參考文獻

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