矽/鍺通道與堆疊穿隧層應用於電荷陷阱式快閃記憶體元件之模擬研究

Simulation Study of Si/Ge Channels and Stacked Tunneling Layer on Charge Trapping Flash Memory Devices

魏鈺庭(Wei, Yu Ting)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/碩士(2016年)

摘要

隨著近年來快閃式記憶體元件的日漸微縮，為了改善元件的操作特性及效能，許多方法被提出，如多晶矽與矽化鍺通道、無接面式通道、堆疊閘極介電層和奈米線結構等等。本論文利用Sentaurus TCAD (Technology Computer Aided Design)模擬軟體工具，模擬平面(二維)與三閘極(三維)的快閃式記憶體元件，探討並比較使用矽、鍺通道與堆疊二氧化鍺/氧化鋁、二氧化矽/氧化鋁、二氧化矽/二氧化鍺和二氧化鍺/氧化鋁/二氧化矽之穿隧層並應用於二維與三維結構的電荷陷阱式快閃記憶體特性。
第一部分為模擬平面多晶矽與矽化鍺通道元件的特性，並與實驗結果做比較。結果發現模擬結果趨勢與實驗不同，因此調整矽化鍺元件的穿隧層參數後再與多晶矽通道元件做比較。修正參數後，矽化鍺元件的寫入與抹除速度變得較快，也與實驗趨勢較符合，而電荷保持力特性的表現因為儲存層有較深的陷阱能階，因此多晶矽通道與矽化鍺通道元件的電荷保持力特性非常相近。
第二部分為了更接近實驗結構而採用三閘極結構快閃式記憶體元件，模擬比較多晶矽、矽化鍺與修正穿隧層參數矽化鍺通道的操作特性。修正穿隧層參數矽化鍺通道的寫入與抹除速度較快，但電荷保持力較多晶矽通道差。接著將三閘極結構模擬結果與平面結構結果做比較，發現三閘極結構有較高的注入效率因此有較快的寫入與抹除速度，並且穿隧層能障效應大過使用三閘極結構，因此適當的穿隧能障和三閘極結構能夠有效提升記憶體元件的操作表現。
第三部分為模擬堆疊穿隧層應用於無接面式矽與鍺通道快閃式記憶體的操作特性。由於較低的通道介面能障、較薄的穿隧層物理厚度以及使用較低介電係數材料的穿隧層堆疊結構，有較快的寫入及抹除速度，但物理厚度薄會有較差的抹除速度和電荷保持力特性。為了在操作特性並與電荷保持力取得平衡，因此使用三層堆疊結構與雙層堆疊結構做比較。三層堆疊結構因為有適當的物理厚度及堆疊組成，因此有較好的記憶體操作特性。

關鍵字

矽鍺通道 ； 電荷陷阱式快閃記憶體元件 ； 堆疊穿隧層 ； TCAD模擬

並列摘要

With the scale down of flash memory devices in recent years, several approaches such as poly-Si channel, SiGe channel, junctionless architecture, stacked gate dielectric and nanowire structure have been proposed to improve the device operation characteristics. In this thesis, Sentaurus TCAD (Technology Computer Aided Design) simulation tool is used to study planer (2D) and tri-gate (3D) flash memory devices. Effects of Si/Ge channels and stacked tunneling layers with GeO2/Al2O3, SiO2/Al2O3, GeO2/SiO2 and GeO2/Al2O3/SiO2 on 2D and 3D charge trapping flash memory devices are investigated and compared.
In the first part, simualted operation characteristics of planer poly-Si and SiGe channel charge-trapping flash memorys are compared to experimental ones. Results show that the trend of the simulation and experiment results are not consistent. Therefore, the physical parameters of tunneling layer of SiGe channel device are modified, and then the simulated results are compared with those of poly-Si channel device. Faster program/erase speeds are achieved by the modified parameters of tunneling layer of SiGe channel device, which shows the same trend as experiment results. The retention characteristics of poly-Si and SiGe devices are similar due to deeper energy level of traps in the trapping layer.
In the second part, tri-gate structures are employed in flash memory devices to simulate operation characteristics because they are exactly used in the experimental devices. Operation characteristics of devices with poly-Si channel and those with SiGe one and modified tunneling layer parameter (MPSiGe) are compared. MPSiGe devices show faster program and erase speeds but worse retention characteristics than poly-Si channel ones. Furthermore, it is found that program/erase speeds of devices with tri-gate structure are faster as compared to those with planer ones because of higher injection efficiency. The influence of tunneling barrier is larger than that of tri-gate structure. Therefore, operation performance of flash memory devices can be enhanced by appropriate tunneling barrier and tri-gate structure.
In the third part, stacked tunneling layer on operation characteristics of junctionless flash memory devices with Si/Ge channel are studied. The program/erase speeds of devices are faster because of lower channel barrier, thinner physical thickness of tunneling layer, and stacked tunneling layer with lower dielectric constant materials. Slow erase speed and poor retention characteristic of devices are due to thinner physical thickness. In order to obtain acceptable performance for all operation characteristics, device with three-layer stacked tunneling oxide is studied, and its results are compared with those of device with two-layer one. Device with three-layer stacked tunneling oxide shows better operation characteristics due to its appropriate physical thickness and stacked structures.

並列關鍵字

Si/Ge channel ； charge-trapping type flash memory ； stacked tunneling ； TCAD Simulaiton

參考文獻

[1] K. San, C. Kaya, and T. Ma, “Effects of Erase Source Bias on Flash EPROM Device Reliability,” in IEEE Electron Device Lett., vol. 42, no. 1, pp. 150-159, January 1995.

[2] M. White, D. Adams, and J. Bu, “on the Go with SONOS,” in IEEE Circuits Devices Mag., vol. 16, no. 4, pp. 22-31, July 2000.

[4] J. Bu, and M. White, “Retention Reliability Enhanced SONOS NVSM with Scaled Programming Voltage,” in Proc. IEEE Aerospace Conf., vol. 5, pp. 5-2383-5-2390, 2002.

[5] K. Kahng, and S. Sze, “A Floating Gate and its Application to Memory Devices,” in IEEE Trans. Electron Devices, vol. 14, no. 9, pp. 629, September 1967.

[8] T. Y. Tseng, and S. M. Sze, “Non-Volatile Memories Materials, Devices, and Applications,” in American Scientific Publishers, Stevenson Ranch, CA, 2012.