垂直型超接面功率金氧半場效電晶體研究

Study On Advanced Power MOSFETs: Vertical Superjunction MOSFET

鄭家慧(Chia-Hui Cheng)

指導教授 ： 黃智方

國立清華大學/電機資訊學院/電子工程研究所/博士(2020年)

摘要

本文研究並提出了一種先進的垂直雙擴散金屬氧化物半導體（VDMOS）功率電晶體。本文使用二維元件模擬評估了VDMOS元件漂移區中Superjunction的使用。Sentaurus中的所有相關物理模型均設置為初始模型並且啟用。從製程模擬中獲得VDMOS元件中相當重要的Superjunction結構的摻雜濃度分佈，並利用量測結果來進行檢驗。本文研究且討論了與Superjunction VDMOS結構在截止狀態崩潰電壓（BV）下的性能以及與特定的導通電阻有關的關鍵的設計參數，以及由雪崩能量EAS定義的非箝位電感負載切換（UIS）能力和元件失效時間。通過調整VDMOS元件漂移區中的Superjunction結構區的磊晶的厚度，可以將導通電阻降低35％，同時保持與基準的Superjunction VDMOS相同的BV。此外，提出了一種新型的深接面終端區，並將其與常規的Floating Guard Ring Termination進行了比較。所提出的結構中的終端區寬度減小了63％，同時保持了相同的崩潰電壓，並使用與常規的元件相同的製程步驟展現了出色的初步高溫反向偏壓（HTRB）可靠性。使用Mixed-mode模擬並通過將主動區Cell和終端區並聯，搭配適當的面積因子，對不同電荷平衡條件下的Superjunction VDMOS的失效進行了數值研究。

關鍵字

垂直型 ； 超接面 ； 功率金氧半場效電晶體

並列摘要

An advanced vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied and is presented in this dissertation. The use of a superjunction in the drift region of a VDMOS device has been evaluated using two-dimensional device simulation. All relevant physical models in Sentaurus are set to default and are enabled. The important doping profiles in the superjunction the VDMOS device are obtained from the process simulation and checked using measurement. Key design parameters related to the performance of the superjunction VDMOS structure in OFF-state breakdown voltage (BV) ,and the specific ON-resistance are examined and discussed, as well as the unclamped inductive load switching (UIS) capability defined based on the avalanche energy EAS and the failure time. By adjusting the thickness of the superjunction epitaxy layer in the drift region of the VDMOS device, the ON-resistance is reduced by 35%, while maintaining the same BV as compared to that of the baseline superjunction VDMOS structure. In addition, a novel deep junction termination method is proposed and compared with the conventional floating guard ring termination. The termination width in the proposed structure is reduced by 63%, while maintaining the same blocking voltage and exhibiting excellent preliminary high temperature reverse bias (HTRB) reliability using the same process steps as a conventional device. The failure of the superjunction VDMOS structure under different charge balance conditions has been numerically studied using mixed-mode simulation and by paralleling the active area cell and the termination with the appropriate area factors.

並列關鍵字

Vertical ； Superjunction ； Power MOSFET

參考文獻

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