相容於邏輯製程之接點耦合閘記憶體研究

The Study of a New MTP Memory Cell with Contact Coupling Gate by a Fully CMOS Compatible Process

連秋旺(Chiu-Wang Lien)

指導教授 ： 林崇榮 ； 金雅琴

國立清華大學/電機資訊學院/電子工程研究所/博士(2013年)

摘要

隨著半導體技術的演進，個人化，可攜帶的電子裝置越來越普及，例如手機、筆記型電腦、數位相機、攝影機。幾乎所有的電子裝置都需要非揮發性的記憶體來儲存程式碼或資料，使重要的資料不會因電池沒電而消失。同時為了方便攜帶，增加產品競爭力，電子裝置越來越輕薄，非揮發性記憶體逐漸由單獨的記憶體晶片轉為內嵌在個別晶片中，以降低電路板的面積。與邏輯製程相比，傳統的非揮發性記憶體元件需要多十幾道光罩與額外的製程步驟，這對良率與可靠度是很大的挑戰。
本論文提出一個可以完全相容於標準邏輯製程的非揮發性記憶體元件，此元件以接點耦合閘的新結構做為控制閘，接點耦合閘是以接點(contact)以及電阻保護氧化層 (RPO)組成，因控制閘是在浮動閘上方，本元件很容易微縮到先進製程。我們在0.18μm的邏輯製程上製造元件以及2Kbits的測試晶片。以通道熱電子注入及FN穿隧效應作為寫入與抹除的機制，藉由接點耦合閘控制浮動閘的電位，我們可以得到快速的寫入與抹除效率。同時在可靠性方面，耐用度 (endurance) 以及資料的保存 (data retention) 也有很好的效能。
本論文提出兩種接點耦合閘的元件，單電晶體的架構可以使記憶體的面積達到最小，適用於大容量非揮發性記憶體的應用，然而對於小容量的嵌入式非揮發性記憶體，雙電晶體的架構會比較適合，因為不需要考慮過度抹除造成位元線漏電的問題，可以簡化周邊電路的設計。由實驗結果，兩種元件都具備很好的寫入、抹除效率以及耐用度與資料可靠度，再加上元件的結構可以很容易微縮到先進製程，本論文所提出的接點耦合閘元件非常適合於邏輯製程相容的非揮發性記憶體的應用。

關鍵字

接點耦合 ； 邏輯非揮發性記憶體 ； 非揮發性記憶體 ； 多次寫入 ； 嵌入式 ； 邏輯相容記憶體

並列摘要

This dissertation proposes a new fully CMOS logic compatible Multi-Time Programmable (MTP) memory cell for serving the high density and low cost requirements of logic non-volatile memory applications. The MTP cell firstly adopts a novel Contact Coupling Gate (CCG) structure as an additional control gate in highly efficient operations and high density memory applications. The new CCG structure is composed of a contact electrode and RPO oxide, which play the roles of control gate and inter-poly oxide in a conventional Stack Gate Flash. The new and small CCG MTP cell has been characterized and proposed to replace the current MTP solution with a larger area or complex or incompatible processes. In terms of the feasibility study, a dense-pitched 2Kbit CCG memory chip has also been successfully demonstrated on a pure 0.18μm CMOS logic process without extra masking or process steps. With the aid of the CCG, a highly efficiently CHE program and FN tunneling erase are achieved and the cell still retains its high cycling endurance and superior data retention. Since the cell size of the CCG MTP can be reduced to 0.808μm2 by a 0.18um CMOS logic design rule, this makes it very suitable for a high density application with fully CMOS logic compatible processes. In summary, with its high performance, low cost, and simple fabrication, the proposed CCG MTP technology is one of the most promising solutions in advanced logic NVM applications.

並列關鍵字

Contact Coupling ； Logic Nonvolatile Memory ； NVM ； Multi-Time Programmable ； Embedded ； Logic Compatible Memory

參考文獻

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