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  • 學位論文

新型邏輯相容水平導通電橋記憶體

A New Lateral Conductive Bridge Random Access Memory by Fully CMOS Logic Compatible Process

指導教授 : 林崇榮 金雅琴
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摘要


隨著可攜式電子產品的普及,對資料儲存產品的需求越來越大。快閃記憶體是非揮發性記憶體在這產業的主流,然後許多的物理上極限使得快閃記憶體的微縮有極大的困難,而新型記憶體中,電阻式記憶體最有機會取代快閃記憶體。 電阻式記憶體與導通電橋式記憶體大多使用邏輯製程不相容的材料,要應用到電路中還需要與製程做整合。本篇論文提出完全使用CMOS製程的新型的側向導通電橋記憶體,記憶節點在contact與poly之間的W/TiN/Ti/poly si水平結構,初始狀態沒有絕緣層的結構可以確定以鈦金屬飄移的轉換機制,雙極性的電阻轉換提供大於10倍的高低阻值比。設置使用1.5V電壓能在50ns內完成操作,重置在-1V的電壓下要5ms的轉態;元件可靠度的方面,讀取干擾能夠確保在10k秒內0.3V不會影響到高阻值態與低阻值態;可以有1k次的設置/重置循環操作;元件在125∘C的環境下能夠保存資料超過1,000個小時而不發生變化。最後使用多晶矽二極體來防止潛行電流,實現一個不做在矽基板上的1D1R結構。良好的操作特性與長時間的可靠度讓創新的LCBRAM可於內嵌多次寫入記憶體的應用。

並列摘要


The requirement of data storage increases with the portable products application. The flash memory dominates the NVM market recently. But the enormous scaling difficulty is countered with physical limit of flash memory. ReRAM is proposed to instead of flash memory in the future. Most of ReRAM and CBRAM are fabricated by the materials which are not compatible with CMOS procces. It is need to be integrated to the CMOS process for the applications. This study proposed a novel fully-logic compatible lateral conductive bridge random access memory. The W/TiN/Ti/poly si memory node is the sidewall structure between poly-si and a CMOS regular contact plug . The Ti-atomic switch mechanism is confirmed by the non-insulator layer structure. The 10 HRS/LRA window is maintained by bipolar switching of LCBRAM . The state switches in 50ns/1.5V set operation and in 5ms/-1V reset operation. The data is not disturbed in 10,000 second by 0.3V read condition. And state can sustain in 1,000 set/reset pulse cycles. No obvious state changes over 1,000 hours amd 125∘C baked. A poly diode is used to prevent the sneak current for 1D1R structure beyond the silicon bulk. Finally, the proposed new cell is a very promising solution for future embedded MTP applications.

參考文獻


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