應用於三維積體電路使用矽穿孔之射頻電路設計

Design of RF circuits with TSVs in 3DIC

籃巧涵(Chiao-Han Lan)

指導教授 ： 徐碩鴻

國立清華大學/電機資訊學院/電子工程研究所/碩士(2013年)

摘要

由於半導體製程的快速進步，伴隨著資料大量傳遞的需求，使得通訊系統不斷的往高速且低功率邁進。然而，元件的尺寸卻隨著縮小而逐漸逼近了物理的極限，且近年來許多高速的通訊規格受到業界與學界的注目，加上未來摩爾定律(Moore’s Law)面臨考驗，三維積體電路(3-Dimentional IC)勢必成為未來整合系統的新趨勢。藉由縱向的三維晶片堆疊，將解決以往二維晶片中連接線過長的問題，也因此可以期待將三維的積體電路技術應用於高速且尺寸小的電路。
然而，在三維積體電路中傳輸高速訊號時，最主要的問題便是矽穿孔(TSV)，因其阻抗與其相連接的二維傳輸線不匹配，容易造成高速訊號位元間的反射干擾(ISI)而形成駐波，進而造成高速訊號傳輸不佳。同時，因矽穿孔(TSV)本身因製程參數不同，側壁二氧化矽對基底之寄生電容也將形成傳導路徑，使得訊號能量在傳輸時將會下降，而造成傳輸訊號損失問題，更甚者，隨著將來TSV直徑逐漸的縮減與深寬比逐漸的加大，這種因阻抗不匹配而使訊號反射的情形將更為嚴重。為了解決上述問題，本論文透過等化器的(equalizer)的技術，將有效地將訊號損耗補償回來。
再者，在研究三維積體電路中的訊號傳輸時，最主要的問題便是如何提升訊號的傳輸速度且保持訊號的完整性(signal integrity)。在一個傳輸系統中，由一條傳輸通道傳一組資料擴增為一條傳輸通道同時傳輸兩組資料，便是一個有效提升速度的方法。利用頻率的不同 (RF及 Baseband)，使兩組訊號傳輸能夠在一個physical通道同時進行，可以大量提升傳輸速度，而每個位元所耗費的功率也明顯降低。此論文將主要研究使用RF Band 的高速傳輸，日後將再與Baseband傳輸整合。在三維積體電路中，使用矽穿孔(TSV)來傳輸可以減少以往利用大量的鎊線(wire-bonding)來連接發射端(transmitter)與傳輸線以及傳輸線與接收端(receiver)，但因製程的取得不易，目前使用flip chip的方式製作。另外，本論文另一重點為立體電感及立體變壓器的設計。對於整體系統來說，晶片面積大小相當重要，因此在本論文中我們將所有的電感及變壓器設計成立體形式，在可以接受的雜訊及功耗範圍內，將面積縮到最小。
在本論文中，共提出了兩個電路及一個RF Band有線傳輸系統。其一為3D被動濾波器，操作頻率為140GHz，損耗小於-3dB，且S11低於-10dB。另一電路為三維積體電路高速資料傳輸之主動式等化器，peaking gain約在2.5GHz，當傳輸速率5Gb/s時，jitter約為22.6ps。而在論文中提出的RF Band有線傳輸系統，傳輸速度約在4Gb/s，jitter約為68ps，面積約為0.3mm2。

關鍵字

被動濾波器 ； 高速資料傳輸 ； 主動式 ； 等化器 ； 三維電感 ； 有線資料傳輸

並列摘要

The rapid progress in semiconductor technology allows the integrated circuits operating with high speed, low power, and complex functions. However, scaling of device feature size is approaching the physical limitation, and the continuation of Moore’s Law becomes questionable. The concept of three-dimensional integrated circuit (3D IC) attracts significant interests recently from both industries and academia. By stacking chips three-dimensionally, the problem of long interconnects in conventional 2D circuits can be resolved, and circuits with high operation speed and small form factors can be expected using 3D IC technology.
However, one major issue for high speed signal transmitting in 3D IC is the Through Silicon Via (TSV). Owing to the limitation of processing technology and pitch size, the impedance mismatch between TSV and 2D transmission line could cause inter-symbol interference (ISI), form a standing wave, and seriously degrade high speed signal transmission. Also, the parasitic capacitances existing between the sidewall oxide layer and the substrate become a conducting path at high frequencies, leading to significant signal loss. These problems could be more pronounced as the TSV pitch size keeps scaling. In this study, we propose of using active equalizer to compensate the signal loss through the TSV in 3DIC for high speed data transmission.
The second issue for high speed signaling in 3D IC is how to further increase the data rate of transmission and also keep the signal integrity. A dual-channel transmission is an effective approach to increase the speed of transmission. Use different frequencies (RF and Baseband), two sets of signal can be transmitted within a physical channel simultaneously. As a result, not only the transmission speed can be increased, but the power consumption of each bit can be reduced significantly. In this study, the signal transmission at the RF frequency will be investigated and will be combined with the baseband transmission in the future. With the 3D IC technology, the through silicon via (TSV) can replace the bond wires to connect the transmitter to the receiver for high speed signaling between different chip layers. The prototype of the circuit is implemented first using the flip chip approach, because of the difficulty to access the 3DIC technology. Another focus of this thesis is the design and optimization of three-dimensional inductors and the transformers for high speed wireline transceivers in 3D IC technology using TSVs. For the overall system, the chip area is a critical design concern. In this project, we will use the 3D inductive components to minimize the chip area with low power consumption and low noise.
In this paper, we propose two circuits and one high speed signal transmission in 3D IC technology. The first circuit is 3D passive fliter, the operating frequency is at 140GHz, loss is less then -3dB, and the S11 is less then -10 dB. Another circuit is a three-dimensional integrated circuit high-speed data transmission active equalizer. The peaking gain is at 2.5GHz. When the transmission rate at 5Gb/s, jitter is about 22.6ps. And the RF band high speed signal transmission in 3D IC technology, which transmission rate at 4Gb/s, jitter is about 68ps, area is about 0.3mm2.

並列關鍵字

pasive filter ； 3D-IC ； High Speed Data Transmission ； Active ； Equalizer ； High Speed Data Transmission, Three-dimensional Inductor, Wireline data transmission system.

參考文獻

[1]E. Beyne, “The rise of the 3rd dimension for system integration,” Interconnect

[2] R.E. Jones, “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, pp. 181-195, 2011.

[3]C. Bermond, L. Cadix, A. Farcy, T. Lacrevaz, P. Leduc, B. Flechet, “High frequency characterization and modeling of high density TSV in 3D integrated circuits,” IEEE Workshop on Signal Propagation on Interconnects, 2009.

[6] S. Gondi, J. Lee, D. Takeuchi, and B. Razavi, “A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications,” IEEE Int. Solid-State Circuits Conf. Tech. Papers, pp. 328-601, 2005.

[7] Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, “A 10 Gb/s receiver with equalizer and on-chip ISI monitor in 0.11 μm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp. 202–205.