Performance and Power Optimization for Power Gating Designs

仇德軒(De-Shiuan Chiou)

指導教授 ： 張世杰

國立清華大學/電機資訊學院/資訊工程學系/博士(2009年)

https://doi.org/10.6843/NTHU.2009.00799

摘要

功率閘控已經成為降低漏電功率的最有效的方法之一。早先被提出的分散式睡眠電晶體網路(Distributed Sleep Transistor Network, DSTN)，藉由串接虛擬接地線來最小化流過睡眠電晶體的瞬時最大電流(Maximum Instantaneous Current, MIC)。在這篇論文裡，我們提出了決定睡眠電晶體大小的方法來最小化漏電功率。
首先，我們提出了一個時間複雜度為O(nlgn)的演算法，來有效估計睡眠電晶體兩端的壓降的上限值。我們的方法並考慮到不同邏輯叢集間放電電流的關連性，藉此避免了過份悲觀的壓降估計。第二，我們把單一一個時脈週期細分為多個時間單元，來觀察瞬時最大電流、壓降、和睡眠電晶體網路三者間的關連性。藉由這層關係，我們針對DSTN架構，提出了縮小睡眠電晶體總面積的演算法。有鑑於在功率閘設計中，常會加上去耦合電容來減少壓降等雜訊，因此我們決定睡眠電晶體大小的方法同時也考慮到了去耦合電容的效應。而針對我們方法的收斂性，我也提出了嚴謹的證明。

關鍵字

功率閘 ； 漏電功率 ； 睡眠電晶體網路

並列摘要

Power gating is one of the most effective ways to reduce leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area for power gating by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current flowing through sleep transistors. In this thesis, we propose two sleep transistor sizing methodologies for leakage power minimization. First, we present an O(n lg n)-time algorithm for efficiently estimating a tight upper bound of the voltage drop across sleep transistors in DSTN structure. Our algorithm takes the correlation between discharge current of different logic clusters into consideration, which avoids over-pessimistic voltage drop estimation. Secondly, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in DSTN designs. In our sizing method, the effect of decoupling capacitances is also taken into account since decaps are commonly inserted in a power gating design to reduce the IR drop noise. Also, the convergence of our sizing algorithm is guaranteed through the theorem we proposed.

並列關鍵字

power gating ； leakage power ； DSTN

參考文獻

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