Growth and Properties of SiGe Virtual Substrates and One-Dimensional Copper-Germanide Nanowires

矽鍺虛擬基材暨一維銅鍺化物奈米線結構成長與性質研究

廖高鋒(Kao-Feng Liao)

指導教授 ： 陳力俊

國立清華大學/工學院/材料科學工程學系/博士(2010年)

摘要

Abstract
Silicon (Si) has been the dominant semiconductor for electronic devices for more than four decades. However, with continued scaling of gate pitch at 0.7× per technology node, the industry has adopted strained Si and high-k dielectric technology to maintain and improve the performance of circuit during the past decade. In addtion, contact resistance and resistance-capacitance delays in the interconnect lines are also important limiting factors for device operation at the same time. Germanium (Ge) is the material with mechanical properties similar to Si. Not only Ge is infinitely soluble in Si, but also, the bulk lattice constant of Ge differs from that of Si by only 4.2%. Hence there has been more research on the use of SiGe and its potential for improving Si device performance. Furthermore, it is easier to combine with the Si-based technology today. In this work, the growth and properties of SiGe virtual substrate and Cu3Ge nanowires have been investigated.
The strain-relaxed SGOI substrate fabricated by Ge condensation is generally regarded to be an appropriate stressor for strained Si epitaxy. Investigations on the oxidation behavior and the post-annealing effect on a strained Si1-xoGexo layer (x0=0.05 and 0.10) grown on 55 nm thick SOI layer of a 8 in. SIMOX wafer were carried out. After dry thermal oxidation at 1000-1050 ℃, thin (<20 nm) SGOI layers with high Ge fraction (x>0.4) were fabricated. In addition, with two-steps oxidation treatment, it could effectively homogenize the Ge distribution in the final relaxed SiGe layer. From examinations of surface morphology of SGOI structures utilizing AFM, it was found that the HF and HCl mixed solution can etch the Ge-oxides much more effectively than only the conventional HF solution.
High-quality, thin relaxed Si0.8Ge0.2 layers grown on Si(100) by ultrahigh-vacuum chemical vapor deposition (UHVCVD) have been formed with hydrogen-implantation and subsequent thermal annealing. H+-implantation was used to introduce a layer with a high density of defects (cavities) below a 200-nm-thick strained Si0.8Ge0.2. The peak of the implanted profile was located just ~50 nm below the Si0.8Ge0.2/Si interface. The dependence of residual strain in pseudomorphic Si0.8Ge0.2 layer on the annealing temperature has been investigated. By adjusting the dose of H+-implantation and the subsequent annealing conditions, almost relaxed (~95%) Si0.8Ge0.2 layers with a smooth surface were achieved. The method provides a simple approach for the formation of thin relaxed Si0.8Ge0.2 with reduction in surface roughness for advanced complementary metal-oxide-semiconductor electronic devices.
Free-standing and single-crystal Cu3Ge nanowires were synthesized by a vapor phase deposition method in one step. The Cu3Ge nanowires are orthorhombic in structure and grown in the [010] direction. The diameters and lengths are about 20-40 nm and 4-8 m, respectively, with aspect ratios of about 200-400. The single-crystal Cu3Ge nanowires exhibit extremely low resistivity of about 4.5-5  cm, the lowest ever for a binary compound. For comparison, the resistivities of Cu3Ge thin films are in the range of 5.5-24  cm. The nanowires can withstand a maximum current density of 3.2×107 A/cm2. It indicates that the Cu3Ge structure can be scaled down to ultrasmall dimensions without degradation of the electrical properties and could be a promising metal contact and interconnect candidate for the fabrication of next generation nanodevices.

摘 要
四十多年來，矽元素在電子元件中一直扮演主流半導體材料的角色。然而，隨著元件尺寸不斷縮小，業界為了維持甚至增強元件的效能，在過去十年間，已經開始採用應變矽技術以及用高介電常數/金屬閘極來取代傳統的二氧化矽/多晶矽閘極。除此之外，在金屬導線間的接觸電阻及R-C延遲效應也同時成為影響元件效能表現的重要一環。鍺元素由於與矽元素性質相近，不僅可以和矽完全互溶，而且晶格常數也僅比矽元素大4.2%，所以有越來越多的研究著重在利用矽鍺合金來增強元件的效能。在本研究中，我們將鍺元素在半導體元件上的應用為主題，探討矽鍺虛擬基材以及具有非常優異的低電阻特性的銅鍺奈米線的結構成長及性質探討。
首先，利用乾式氧化法使鍺元素濃度提升的方法，可形成應變鬆弛的絕緣層上的矽鍺層，並可被用來當作應變矽的應變源。一開始，在長有55奈米厚的矽層的SIMOX晶片上先成長具有不同鍺起始濃度的矽鍺層，本研究將探討不同的乾式氧化及後續退火條件對於應變鬆弛的絕緣層上矽鍺層的影響。在經過適當條件的氧化及退火處理後，厚度小於20奈米且具有高鍺濃度的應變鬆弛的絕緣層被成功的製備。此外，我們發現藉由兩階段退火處理，可有效的改善起始鍺濃度較高的試片在氧化後所面臨的鍺分佈不均的現象。而在利用原子力顯微鏡探討應變鬆弛的絕緣層上矽鍺層的表面平整度時，發現利用氫氟酸及鹽酸的混和液可以比傳統的單純氫氟酸更有效的去除表面的鍺氧化物的雜粒。
在第二部份研究中，利用超高真空化學氣相沉積法所成長的矽鍺層可藉由氫離子佈植法及後續的退火處理來促使應變鬆弛。在此方法中，氫離子佈植在矽鍺層與矽基材界面的下方約50奈米處。藉由改變不同的佈植濃度及不同的退火條件，將可以成功製備近乎完全應變鬆弛且具有平整界面的矽鍺層。此方法提供一個較簡易的方法來製備可以適用於先進元件的應變鬆弛矽鍺層。
在第三部份研究中，利用氣相傳輸法，獨立於試片表面且單晶結構的銅鍺奈米線第一次成功被製備。本研究所製備的銅鍺奈米線具有長方晶的單晶結構，並且沿著[010]方向成長。銅鍺奈米線的粗細範圍多介於20-40奈米且長度介於4-8微米，換算所得的長寬比則介於200-400間。特別的是，本研究所製備的銅鍺奈米線具有相當優異的低電阻性質（4.5-5  cm）以及3.2×107 A/cm2的高電流密度。在現今已製備的二元化合物的奈米線中，具有最低的電阻率。除此之外，與薄膜型態的銅鍺化合物相比，銅鍺奈米線在尺寸微縮後，仍具有相當優異的電阻率，這些特性對於銅鍺奈米線在日後應用於金屬接觸及金屬間導線上具有相當大的優勢。

關鍵字

矽鍺 ； 銅鍺化物奈米線 ； 電阻率

並列摘要

無資料

並列關鍵字

SiGe ； Copper Germanide Nanowires ； Electrical Resistivity

參考文獻

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