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  • 學位論文

Investigation of Reliability Issues in a SONOS Flash Memory Cell

矽氧化氮氧化矽快閃記憶元件可靠度問題之研究

指導教授 : 洪勝富
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摘要


在本論文中,我們提出一個新型的可變振幅低頻式電荷幫浦 (VALFCP)技術 來描述矽氧化氮氧化矽 (SONOS) 快閃記憶元件中氮化矽層缺陷的能量和空間分布。此外,亦使用此VALFCP 技術來研究氧化層和氮化矽層的缺陷經過多次的資料寫入∕抹除操作後的特性。我們也利用二維 TCAD模擬器來探討分離摻雜物擾動對於SONOS 元件保存能力的影響。 在第二章中,我們提出了新型的VALFCP 技術,此技術包含一改良後的電荷幫浦量測方法論和一數值模型,可以從電荷幫浦量測資料中萃取出空間和能量的缺陷分布。此數值模型根據Shockley-Read-Hall-like 電荷穿隧捕捉,使電荷幫浦電流和氮化矽缺陷的能量和空間分布產生關聯性。改變電荷幫浦量測方法的頻率和脈衝振幅,可以萃取出以缺陷空間和能量為函數的氮化矽層缺陷密度。在第三章中,我們利用VALFCP 技術來探討在SONOS快閃記憶元件中多次的資料寫入∕抹除操作對缺陷產生的影響。我們觀察到在多次的資料寫入∕抹除操作後會在氧化層和氮化矽層產生新的缺陷,也會對元件保存能力造成極大的衰退。氧化層和氮化矽層的缺陷密度的增加量遵守指數定律並以資料寫入∕抹除次數為函數。我們也觀察到經由寫入以及抹除操作後所產生的氧化層和氮化矽層的缺陷是不穩定的,且高溫儲存的過程中會迅速逸失。 在第四章中,探討分離摻雜物擾動對於45奈米世代以下SONOS為結構之快閃記憶元件的影響。除了已知臨界電壓的擾動之外,寬廣的臨界電壓分布也會影響元件的保存能力,並導致在22奈米世代以下,平面型SONOS快閃記憶元件嚴重的可靠度問題。本篇論文也探討了分離摻雜物擾動對於鰭式場效電晶體 (FinFET) 的影響。具有幾乎無摻雜物通道的FinFET SONOS快閃記憶元件驗證可成為22奈米世代以下 SONOS技術的趨勢。

並列摘要


In this dissertation, we propose a new VALFCP (variable amplitude low-frequency charge pumping) technique to characterize the nitride trap energy and spatial distributions in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory cells. Besides, the VALFCP technique is utilized to investigate effects of P/E cycles on nitride/oxide trap properties. We also study the effects of dopant fluctuation on SONOS cell retention by using 2D TCAD simulations. In chapter 2, we propose a new VALFCP technique including a modified charge pumping measurement methodology and a generalized numerical model, which allows extracting the spatial and energy trap distributions from the charge pumping data. A numerical model based on Shockley-Read-Hall-like electron tunneling capture is used to correlate a charge pumping current with nitride trap energy and position. By changing frequency and pulse amplitude in charge pumping measurement, a nitride trap density as a function of trap position and energy can be extracted. In chapter 3, influences of program/erase (P/E) cycles on the defect generation in a SONOS flash memory cell are studied by using the VALFCP technique. We observe that P/E cycles would generate new oxide and nitride traps, and degraded cell retention is observed. Besides, the increase of oxide and nitride trap densities follows a power law behavior as a function of P/E cycles. We also observe that these stress-created oxide and nitride traps are unstable and will be eliminated rapidly during high temperature storage. In chapter 4, the effects of discrete dopant fluctuation in sub-45-nm SONOS flash memory cells are studied. In addition to the well-known fluctuation in threshold voltage, the wide threshold voltage distribution also affects cell retention, which results in a severe reliability problem in planar SONOS flash memory cells beyond the 22 nm generation. Similar discrete dopant effects are observed in the fin field-effect transistor (FinFET) structure. The FinFET SONOS flash memory cell having a nearly un-doped channel is shown to be promising for sub-22-nm SONOS technologies.

並列關鍵字

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參考文獻


Chapter 1
[1] K. Kim, “Technology for sub 50-nm node DRAM and NAND Flash Manufacturing,” IEEE IEDM Tech. Dig., pp. 323-326, 2005.
[2] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11, pp. 543-545, Nov. 2000.
[7] W. D. Brown and J. E. Brewer, Eds., Nonvolatile Semiconductor Memory Technology. Piscataway, NJ: IEEE Press, 1998.
[8] Tahui Wang, W.J. Tsai, S.H. Gu, C.T. Chan, C.C. Yeh, N.K. Zous, T.C. Lu, S. Pan, and C.Y. Lu, “Reliability Models of Data Retention and Read-Disturb in 2-Bit Nitride Storage Flash Memory Cells,” IEEE IEDM Tech. Dig., pp. 169-172, 2003.

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