適用於多輸入多輸出正交分頻多工系統之高硬體效率快速傅立葉轉換處理器

Design of a Hardware-Efficient FFT Processor for MIMO OFDM Systems

蔡志墝(Chih-Chiao Tsai)

指導教授 ： 張慶元

國立清華大學/電機資訊學院/電機工程學系/碩士(2010年)

摘要

現今，無線通訊系統在人們的生活當中扮演非常重要的角色。而因應越來越龐大的多媒體資料傳輸需求，相繼衍生出多種通訊技術，其中多輸入多輸出與正交分頻多工技術，被廣泛的使用。而快速傅立葉轉換處理器在所有多輸入多輸出正交分頻多工的通訊系統中是關鍵性的模組。因而，快速傅立葉轉換處理器必須有處理多個平行資料序列的能力。在傳統上是採用多個快速傅立葉轉換處理器來處理多個平行資料序列，但是會造成較差的硬體效率與較高的功率消耗。因此，將多個快速傅立葉轉換處理器整合在一起，達到硬體資源共享，以提高硬體效率與降低功率消耗是現今的趨勢。
在本篇論文中，我們提出一個基於增強的IEEE 802.11n標準之應用於多輸入多輸出正交分頻多工系統之高硬體效率快速傅立葉轉換處理器。此處理器是採用MRM^2DF(Mixed-Radix Mixed-Multipath Delay Feedback)架構，其使用多資料路徑結構來提供高輸出率，並且採用radix-2和radix-2^3演算法來降低硬體複雜度。此外利用保護區間來增加處理兩條平行資料序列的能力。因此平行路徑的數目從四條延伸至六條，且採用共用硬體資源的方法來降低硬體面積和功率消耗。我們使用UMC 90-nm 1P9M製程實現所提出的處理器，其面積為739 x 734 (um)^2，且在40MHz的操作頻率下消耗功率為5.57 mW，SQNR為40.17dB。此處理器符合增強的IEEE 802.11n標準，能在40MHz的操作頻率下，同時處理在3.2us內的六條獨立的FFT資料序列。

關鍵字

多輸入多輸出 ； 正交分頻多工 ； 快速傅立葉轉換 ； 多路徑延遲回授

並列摘要

Wireless communication plays a significant role in people’s life nowadays, and the response to an ever-growing demand for multimedia data transmission, have spawned a variety of communications technologies, including multiple-input multiple-output (MIMO), orthogonal frequency division multiplexing (OFDM) technology, has been widely used. The FFT Processor is the key module in the all MIMO OFDM communication systems. Therefore, the FFT processor must have the capacity of dealing with the simultaneous multiple data sequences. Adopting several FFT processors to process the simultaneous multiple data sequences, the traditional approach results in lower hardware efficiency and higher power consumption. Therefore, multiple FFT processors integrated to achieve the sharing of hardware resources in order to increase hardware efficiency and to reduce power consumption are the current trend.
In this thesis, we proposed a hardware-efficient 128-point FFT processor for the applications in a MIMO OFDM based enhancement of IEEE 802.11n standard. Our processor is adopts the mixed-radix mixed-multipath delay feedback (MRM^2DF) architecture, which provides a higher throughput rate by using the multi-data path scheme, and radix-2 and radix-2^3 algorithm are adopted to reduce hardware complexity. Furthermore, it utilizes the guard interval to increase the capacity of dealing with two parallel data sequences. Thus, the number of parallel paths is extended from four to six. The proposed FFT processor is implemented in UMC 90-nm 1P9M process with core area of 739 x 734 (um)^2 including an FFT processor and a test module. The power consumption is 5.57 mW at 40MHz operating frequency, and SQNR is 40.17dB. At the operation clock rate of 40Mhz, our proposed processor can calculate 128-point FFT with six independent data sequences within 3.2 us meeting the enhancement of IEEE 802.11n standard requirements.

並列關鍵字

MIMO ； OFDM ； FFT ； MDF

參考文獻

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