透過您的圖書館登入
IP:3.144.33.41
  • 學位論文

應用於低功耗大數據處理之過濾式搜尋引擎-可快速開機常關型之非揮發性三元內容循址記憶體

A Normally-off Instant-on Stress-relieved Nonvolatile TCAM for Filter-based Search Engines Used in Energy-Efficient Big-Data Processing

指導教授 : 張孟凡
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


隨著嵌入式系統與網路的快速發展,世界各處無時無刻產生大量資料,新興電子應用(如:智慧型手機、平板、無線感測網絡、辨識系統以及物聯網等)有著需處理大量資料、待機時間長之特性,並有低耗能的需求;我們認為當未來大數據時代中,雲端運算進行多筆資料傳輸、複雜運算耗能之大,若增加一過濾器如:三元內容循址記憶體於各種平台介面間,可先將接收到的資料進行快速比對過濾,就能大幅減少高耗能後傳處理的資料量,達到省能效用.   然而此過濾器需適應這些新興應用的特色-1.容量需求大 2.待機時間長;傳統靜態隨機存取器為基底的三元內容循址記憶體需要兩組靜態隨機存取器儲存三種資料、為16顆電晶體組成的記憶胞,使得系統面積有限的情況下容量小;此外因製程微縮靜態隨機存取器之待機漏電耗能的頭疼問題,一般解決方法為將資料搬動到另外一塊非揮發性記憶體內,然而這個作法不但開關機需搬動資料耗能大,且受限於傳輸介面的輸入輸出端數、導致開關機資料搬動時間隨容量而增加。   論文欲結合新興非揮發性記憶體進行改良,電阻式記憶體為相當具有潛力的非揮發記憶元件,特色為高密度、高低阻態比值大、可快速隨機存取且不會有長時間儲存後阻值漂移的問題,然而若為了較快讀取速度或較大感測邊界而施加較大讀取電壓,使電阻式記憶體長時間兩端跨壓大,則可能造成阻值漂移,嚴重時會造成讀取錯誤.稱之為讀取干擾;因此做高速電路設計須考慮讀取干擾造成的資料可靠度問題.   論文提出一電阻電容過濾式降壓4T2R非揮發性三元內容循址記憶體,達到: 1. 降低配對限於配對情況的漏電電流. 2. 降低配對線負載 3. 創新的電阻電容延遲搜尋方式,可使搜尋時電阻式記憶體的讀取壓力(流經電阻式記憶體的電流對時間積分)比起目前國際論文已發表之架構小約6倍,緩和讀取壓力與搜尋速度之間的取捨。 4. 提升4倍的品質因素:速度乘以可支援最常配對線長度乘以容量.   於0.18微米邏輯製程下、4千位元的非揮發性三元內容循址記憶體實體晶片達到搜尋時間為1.2奈秒。

並列摘要


With the rapid growth of the internet and embedded systems, large amounts of data are created everywhere in the world simultaneously. Emerging Electronic Applications (ex. Smart Phones, PADs, wireless sensing networks, recognition systems and Internet of things) have characteristics including large amounts of data waiting to be processed, long standby time, and need for low energy. We believe that in the era of big data, energy caused by the large amount of data transfers and complex computations Cloud computing generates could be greatly reduced by introducing a filter like Ternary Content Addressable Memory (TCAM) between different platforms. This kind of memory can compare and filter incoming data, thus reducing the amount of data sent to following stages and save power.   However, this kind of filter needs to fulfill the needs of these emerging applications - 1.Large Capacity, 2.long standby time. Traditional Static Random Access Memory (SRAM)-based TCAM needs two pairs of SRAM cells to save 3 states of data (0, 1 and don’t care). Under the same area constraint, SRAM-based TCAM (16T) has a small capacity; In addition, with process scaling down the leakage problem caused by SRAM also appears in TCAM. Conventional solution moves the stored data to another nonvolatile memory macro (NVM macro), but this method not only requires large energy for moving data, but is also a slow process limited by the I/O number of the interface.   This study plans to improve current solutions by combining emerging NVM with CMOS process in cell level. Resistive Random Access Memory (ReRAM ) is a very promising nonvolatile memory, with high density, distinctive states ( high R-Ratio) , fast random access, and good data retention time. However, a large voltage may be placed across the ReRAM for fast access, which may cause the ReRAM resistance to drift, and could lead to read failure under serious conditions. This situation (Read Disturb) must be put into consideration when designing high-speed ReRAM circuits.   This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 6x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128x32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) search delay (TSD) among nvTCAMs with WDL≧32bits.

並列關鍵字

Big data processing NVM TCAM

參考文獻


[8] G. De Sandre, et al., "A 90nm4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 268-269, Feb. 2010.
[9] T. Morikawa, et al., "A low power phase change memory using low thermal conductive doped-Ge2Sb2Te 5 with nano-crystalline structure," IEEE International Electron Devices Meeting (IEDM), pp. 3141-3144, Dec. 2012.
[10] H. Y. Cheng , et al., "A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change 58 material," IEEE International Electron Devices Meeting (IEDM), pp. 341-344, Dec. 2011.
[11] F. Bedeschi, et al., "A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage," IEEE Journal of Solid-State Circuits, vol. 44, pp. 217-227, Jan. 2009.
[12] J. Y. Wu, et al., "A low power phase change memory using thermally confined TaN/TiN bottom electrode," IEEE International Electron Devices Meeting (IEDM), pp. 321-324, Dec. 2011.

延伸閱讀