- 學位論文
整合揮發性磁記憶體與緩衝區設計之適應性更新機制快取記憶體
Adaptive Refresh Cache Design with Volatile STT-RAM and SRAM Buffering
摘要
磁記憶體(Spin-Transfer Torque random access memory ─ STT-RAM)有著高 密度及很低的能源耗損兩項優點，但是他的寫入延遲與寫入耗能非常的高。藉 由縮小磁記憶體的資料保存時間可以改善寫入延遲與寫入耗能兩項缺點，但是 這樣又會需要頻繁的刷新動作來避免資料遺失，造成額外的能源耗損。 本論文中，我們提出適應性更新機制並整合靜態隨機存取記憶體(static random access memory ─ SRAM)與揮發性STT-RAM來作為最底層的快取記憶 體。首先資料區塊先對映到SRAM上，因為SRAM有較低的寫入延遲與寫入耗能， 之後再搬移到揮發性STT-RAM避免在SRAM所造成的高能源耗損。當資料區塊 經過一段時間都沒有被存取時就停止對該區塊做刷新的動作，這樣可以減少揮 發性 STT-RAM因為刷新動作太頻繁我造成的能源消耗。在這快取架構跟刷新機 制下，我們可以由實驗結果證明，我們的方法結合揮發性STT-RAM低能源耗損 的優點，跟傳統SRAM快取相比可以有更小的能源消耗跟更高的密度。跟揮發性 STT-RAM相比也因為結合SRAM使得可以降低非常大的寫入延遲。
並列摘要
Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and ignorable leakage power. However, it suffers from the bad write latency and poor write power consumption. Relaxing the retention time of STT-RAM cell can improve the write performance, but volatile STT-RAM would dissipate extra energy due to frequent refresh operations. In this paper, we propose an adaptive refresh methodology for L1 cache design with integrated SRAM and volatile STT-RAM architecture. Data block is mapped to SRAM firstly to reduce write latency, and is moved to volatile STT-RAM when it would be replaced to reduce leakage power consumption. After a time period when there is no access of a data block in the volatile STT-RAM, we then stop its refresh operations to further reduce extra energy consumption. With this cache architecture design and refresh methodology, experimental results show that we get better energy consumption than fully SRAM based cache design because of less leakage power, and also we have better performance latency because of compatible write performance with SRAM and higher cache hit rate due to higher STT-RAM circuit density.
參考文獻
延伸閱讀
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